[GIT PULL] u-boot-riscv/next

[Leo Liang <ycliang@andestech.com>]

Hi Tom,

The following changes since commit c405bab7661dd60420e97a4edeb3162e9d7e02c5:

  Merge tag 'mmc-next-2025-07-02' of https://source.denx.de/u-boot/custodians/u-boot-mmc into next (2025-07-02 07:51:57 -0600)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git next

for you to fetch changes up to f62062a64daeb3f3b148372d0afae3821aff16de:

  cache: Update dependency for ANDES_L2_CACHE (2025-07-03 18:11:06 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/26936
----------------------------------------------------------------
- RISC-V: Add big-endian build support
- Board: aclint_ipi: Support T-Head C900 CLINT
- Board: mpfs_icicle: Implement board_fdt_blob_setup()/board_fit_config_name_match()
- Driver: pinctrl: Port pin controller driver for T-Head TH1520 SoC
- Driver: cache: Update dependency for ANDES_L2_CACHE
----------------------------------------------------------------
Ben Dooks (2):
      riscv: add build support for big-endian
      riscv: byteorder: add test for big-endian

Conor Dooley (1):
      board: mpfs_icicle: implement board_fdt_blob_setup()/board_fit_config_name_match()

Tom Rini (1):
      cache: Update dependency for ANDES_L2_CACHE

Yao Zi (8):
      riscv: aclint_ipi: Support T-Head C900 CLINT
      riscv: cpu: th1520: Setup CPU feature CSRs in harts_early_init
      riscv: cpu: th1520: Add a routine to bring up secondary cores
      riscv: dts: th1520: Preserve CLINT node for SPL
      board: thead: licheepi4a: Bring up secondary cores in SPL
      pinctrl: Port pin controller driver for T-Head TH1520 SoC
      riscv: dts: th1520: Add pin controllers
      riscv: cpu: th1520: Enable pinctrl by default

 MAINTAINERS                               |   1 +
 arch/riscv/config.mk                      |  18 +-
 arch/riscv/cpu/th1520/Kconfig             |   1 +
 arch/riscv/cpu/th1520/cpu.c               |  29 +-
 arch/riscv/cpu/th1520/spl.c               |  83 ++++
 arch/riscv/dts/th1520.dtsi                |  29 ++
 arch/riscv/include/asm/arch-th1520/cpu.h  |   1 +
 arch/riscv/include/asm/byteorder.h        |   2 +-
 arch/riscv/lib/aclint_ipi.c               |   5 +
 board/microchip/mpfs_icicle/mpfs_icicle.c |  63 +++
 board/thead/th1520_lpi4a/spl.c            |   3 +
 configs/th1520_lpi4a_defconfig            |   1 +
 drivers/cache/Kconfig                     |   1 +
 drivers/pinctrl/Kconfig                   |   8 +
 drivers/pinctrl/Makefile                  |   1 +
 drivers/pinctrl/pinctrl-th1520.c          | 700 ++++++++++++++++++++++++++++++
 16 files changed, 940 insertions(+), 6 deletions(-)
 create mode 100644 drivers/pinctrl/pinctrl-th1520.c

Best regards,
Leo