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From: Leo Liang <ycliang@andestech.com>
To: Zong Li <zong.li@sifive.com>
Cc: <rick@andestech.com>, <peterlin@andestech.com>, <u-boot@lists.denx.de>
Subject: Re: [PATCH 1/2] cache: add sifive private L2 cache driver
Date: Thu, 21 Dec 2023 18:02:56 +0800	[thread overview]
Message-ID: <ZYQNPZ26huRiabQ6@swlinux02> (raw)
In-Reply-To: <20231214140937.27784-2-zong.li@sifive.com>

On Thu, Dec 14, 2023 at 02:09:36PM +0000, Zong Li wrote:
> This driver is currently responsible for enabling the clock gating
> feature of SiFive pre core's private L2 cache.
> 
> Signed-off-by: Zong Li <zong.li@sifive.com>
> ---
>  drivers/cache/Kconfig            |  7 +++++
>  drivers/cache/Makefile           |  1 +
>  drivers/cache/cache-sifive-pl2.c | 44 ++++++++++++++++++++++++++++++++
>  3 files changed, 52 insertions(+)
>  create mode 100644 drivers/cache/cache-sifive-pl2.c

Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

  reply	other threads:[~2023-12-21 10:03 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-14 14:09 [PATCH 0/2] Add SiFive private L2 cache driver Zong Li
2023-12-14 14:09 ` [PATCH 1/2] cache: add sifive " Zong Li
2023-12-21 10:02   ` Leo Liang [this message]
2023-12-14 14:09 ` [PATCH 2/2] riscv: cache: support cache enable in SPL stage Zong Li
2023-12-21 10:03   ` Leo Liang

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