From: Leo Liang <ycliang@andestech.com>
To: Zong Li <zong.li@sifive.com>
Cc: <rick@andestech.com>, <peterlin@andestech.com>, <u-boot@lists.denx.de>
Subject: Re: [PATCH 2/2] riscv: cache: support cache enable in SPL stage
Date: Thu, 21 Dec 2023 18:03:22 +0800 [thread overview]
Message-ID: <ZYQNalNhp8294NMy@swlinux02> (raw)
In-Reply-To: <20231214140937.27784-3-zong.li@sifive.com>
On Thu, Dec 14, 2023 at 02:09:37PM +0000, Zong Li wrote:
> The power gating feature of pl2 should be enabled as early as possible,
> it would be better to put it in SPL stage.
>
> Signed-off-by: Zong Li <zong.li@sifive.com>
> ---
> arch/riscv/lib/sifive_cache.c | 21 +++++++++++++++++++++
> 1 file changed, 21 insertions(+)
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
prev parent reply other threads:[~2023-12-21 10:03 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-14 14:09 [PATCH 0/2] Add SiFive private L2 cache driver Zong Li
2023-12-14 14:09 ` [PATCH 1/2] cache: add sifive " Zong Li
2023-12-21 10:02 ` Leo Liang
2023-12-14 14:09 ` [PATCH 2/2] riscv: cache: support cache enable in SPL stage Zong Li
2023-12-21 10:03 ` Leo Liang [this message]
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