From: Yu-Chien Peter Lin <peterlin@andestech.com>
To: Leo Yu-Chi Liang <ycliang@andestech.com>
Cc: <u-boot@lists.denx.de>, <randolph@andestech.com>
Subject: Re: [PATCH v2 1/6] andes: csr.h: Clean up CSR definition
Date: Tue, 26 Dec 2023 15:33:02 +0800 [thread overview]
Message-ID: <ZYqBo-51BudcSvJD@APC323> (raw)
In-Reply-To: <20231226061736.482416-1-ycliang@andestech.com>
On Tue, Dec 26, 2023 at 02:17:32PM +0800, Leo Yu-Chi Liang wrote:
> Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
> arch/riscv/include/asm/arch-andes/csr.h | 20 ++++++++------------
> arch/riscv/include/asm/csr.h | 1 +
> 2 files changed, 9 insertions(+), 12 deletions(-)
>
> diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h
> index 393d51c6dd..12d5eb6f6c 100644
> --- a/arch/riscv/include/asm/arch-andes/csr.h
> +++ b/arch/riscv/include/asm/arch-andes/csr.h
> @@ -12,20 +12,16 @@
>
> #define CSR_MCACHE_CTL 0x7ca
> #define CSR_MMISC_CTL 0x7d0
> -#define CSR_MARCHID 0xf12
> #define CSR_MCCTLCOMMAND 0x7cc
>
> -#define MCACHE_CTL_IC_EN_OFFSET 0
> -#define MCACHE_CTL_DC_EN_OFFSET 1
> -#define MCACHE_CTL_CCTL_SUEN_OFFSET 8
> -#define MCACHE_CTL_DC_COHEN_OFFSET 19
> -#define MCACHE_CTL_DC_COHSTA_OFFSET 20
> -
> -#define MCACHE_CTL_IC_EN BIT(MCACHE_CTL_IC_EN_OFFSET)
> -#define MCACHE_CTL_DC_EN BIT(MCACHE_CTL_DC_EN_OFFSET)
> -#define MCACHE_CTL_CCTL_SUEN BIT(MCACHE_CTL_CCTL_SUEN_OFFSET)
> -#define MCACHE_CTL_DC_COHEN BIT(MCACHE_CTL_DC_COHEN_OFFSET)
> -#define MCACHE_CTL_DC_COHSTA BIT(MCACHE_CTL_DC_COHSTA_OFFSET)
> +/* mcache_ctl register */
> +
> +#define MCACHE_CTL_IC_EN BIT(0)
> +#define MCACHE_CTL_DC_EN BIT(1)
> +#define MCACHE_CTL_CCTL_SUEN BIT(8)
> +#define MCACHE_CTL_DC_COHEN BIT(19)
> +#define MCACHE_CTL_DC_COHSTA BIT(20)
> +
>
> #define CCTL_L1D_WBINVAL_ALL 6
>
> diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
> index 1a15089cae..986f951c31 100644
> --- a/arch/riscv/include/asm/csr.h
> +++ b/arch/riscv/include/asm/csr.h
> @@ -142,6 +142,7 @@
> #define CSR_CYCLEH 0xc80
> #define CSR_TIMEH 0xc81
> #define CSR_INSTRETH 0xc82
> +#define CSR_MARCHID 0xf12
> #define CSR_MHARTID 0xf14
>
> #ifndef __ASSEMBLY__
> --
> 2.34.1
>
prev parent reply other threads:[~2023-12-26 7:33 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-26 6:17 [PATCH v2 1/6] andes: csr.h: Clean up CSR definition Leo Yu-Chi Liang
2023-12-26 6:17 ` [PATCH v2 2/6] andes: ae350: Implement cache switch via Kconfig Leo Yu-Chi Liang
2023-12-26 7:34 ` Yu-Chien Peter Lin
2023-12-26 6:17 ` [PATCH v2 3/6] andes: cpu: Enable memboost feature Leo Yu-Chi Liang
2023-12-26 7:42 ` Yu-Chien Peter Lin
2023-12-26 6:17 ` [PATCH v2 4/6] andes: cpu: Enable cache and TLB ECC support Leo Yu-Chi Liang
2023-12-26 7:43 ` Yu-Chien Peter Lin
2023-12-26 7:33 ` Yu-Chien Peter Lin [this message]
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