Re: [PATCH v2 2/6] andes: ae350: Implement cache switch via Kconfig

[Yu-Chien Peter Lin <peterlin@andestech.com>]

On Tue, Dec 26, 2023 at 02:17:33PM +0800, Leo Yu-Chi Liang wrote:
> Kconfig provides SYS_[I|D]CACHE_OFF config options to switch off caches.
> Provide the corresponding implementation to the options.
> 
> Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>

Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>

> ---
>  arch/riscv/cpu/andesv5/cpu.c  | 25 ++++++++++++++++---------
>  board/AndesTech/ae350/ae350.c |  3 ++-
>  2 files changed, 18 insertions(+), 10 deletions(-)
> 
> diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5/cpu.c
> index 63bc24cdfc..e764f6c5c0 100644
> --- a/arch/riscv/cpu/andesv5/cpu.c
> +++ b/arch/riscv/cpu/andesv5/cpu.c
> @@ -32,18 +32,25 @@ void harts_early_init(void)
>  	if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
>  		unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
>  
> -		mcache_ctl_val |= (MCACHE_CTL_DC_COHEN | MCACHE_CTL_IC_EN |
> -				   MCACHE_CTL_DC_EN | MCACHE_CTL_CCTL_SUEN);
> +		mcache_ctl_val |= MCACHE_CTL_CCTL_SUEN;
> +
> +		if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF))
> +			mcache_ctl_val |= MCACHE_CTL_IC_EN;
> +
> +		if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
> +			mcache_ctl_val |= (MCACHE_CTL_DC_EN | MCACHE_CTL_DC_COHEN);
>  
>  		csr_write(CSR_MCACHE_CTL, mcache_ctl_val);
>  
> -		/*
> -		 * Check mcache_ctl.DC_COHEN, we assume this platform does
> -		 * not support CM if the bit is hard-wired to 0.
> -		 */
> -		if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) {
> -			/* Wait for DC_COHSTA bit to be set */
> -			while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA));
> +		if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) {
> +			/*
> +			 * Check mcache_ctl.DC_COHEN, we assume this platform does
> +			 * not support CM if the bit is hard-wired to 0.
> +			 */
> +			if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) {
> +				/* Wait for DC_COHSTA bit to be set */
> +				while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA));
> +			}
>  		}
>  	}
>  }
> diff --git a/board/AndesTech/ae350/ae350.c b/board/AndesTech/ae350/ae350.c
> index 772c6bf1ee..bef9e3149e 100644
> --- a/board/AndesTech/ae350/ae350.c
> +++ b/board/AndesTech/ae350/ae350.c
> @@ -102,7 +102,8 @@ void *board_fdt_blob_setup(int *err)
>  void spl_board_init()
>  {
>  	/* enable v5l2 cache */
> -	enable_caches();
> +	if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
> +		enable_caches();
>  }
>  #endif
>  
> -- 
> 2.34.1
>