* [PATCH v2 2/6] andes: ae350: Implement cache switch via Kconfig
2023-12-26 6:17 [PATCH v2 1/6] andes: csr.h: Clean up CSR definition Leo Yu-Chi Liang
@ 2023-12-26 6:17 ` Leo Yu-Chi Liang
2023-12-26 7:34 ` Yu-Chien Peter Lin
2023-12-26 6:17 ` [PATCH v2 3/6] andes: cpu: Enable memboost feature Leo Yu-Chi Liang
` (2 subsequent siblings)
3 siblings, 1 reply; 8+ messages in thread
From: Leo Yu-Chi Liang @ 2023-12-26 6:17 UTC (permalink / raw)
To: u-boot; +Cc: ycliang, randolph, peterlin
Kconfig provides SYS_[I|D]CACHE_OFF config options to switch off caches.
Provide the corresponding implementation to the options.
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
arch/riscv/cpu/andesv5/cpu.c | 25 ++++++++++++++++---------
board/AndesTech/ae350/ae350.c | 3 ++-
2 files changed, 18 insertions(+), 10 deletions(-)
diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5/cpu.c
index 63bc24cdfc..e764f6c5c0 100644
--- a/arch/riscv/cpu/andesv5/cpu.c
+++ b/arch/riscv/cpu/andesv5/cpu.c
@@ -32,18 +32,25 @@ void harts_early_init(void)
if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
- mcache_ctl_val |= (MCACHE_CTL_DC_COHEN | MCACHE_CTL_IC_EN |
- MCACHE_CTL_DC_EN | MCACHE_CTL_CCTL_SUEN);
+ mcache_ctl_val |= MCACHE_CTL_CCTL_SUEN;
+
+ if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF))
+ mcache_ctl_val |= MCACHE_CTL_IC_EN;
+
+ if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+ mcache_ctl_val |= (MCACHE_CTL_DC_EN | MCACHE_CTL_DC_COHEN);
csr_write(CSR_MCACHE_CTL, mcache_ctl_val);
- /*
- * Check mcache_ctl.DC_COHEN, we assume this platform does
- * not support CM if the bit is hard-wired to 0.
- */
- if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) {
- /* Wait for DC_COHSTA bit to be set */
- while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA));
+ if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) {
+ /*
+ * Check mcache_ctl.DC_COHEN, we assume this platform does
+ * not support CM if the bit is hard-wired to 0.
+ */
+ if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) {
+ /* Wait for DC_COHSTA bit to be set */
+ while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA));
+ }
}
}
}
diff --git a/board/AndesTech/ae350/ae350.c b/board/AndesTech/ae350/ae350.c
index 772c6bf1ee..bef9e3149e 100644
--- a/board/AndesTech/ae350/ae350.c
+++ b/board/AndesTech/ae350/ae350.c
@@ -102,7 +102,8 @@ void *board_fdt_blob_setup(int *err)
void spl_board_init()
{
/* enable v5l2 cache */
- enable_caches();
+ if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+ enable_caches();
}
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v2 2/6] andes: ae350: Implement cache switch via Kconfig
2023-12-26 6:17 ` [PATCH v2 2/6] andes: ae350: Implement cache switch via Kconfig Leo Yu-Chi Liang
@ 2023-12-26 7:34 ` Yu-Chien Peter Lin
0 siblings, 0 replies; 8+ messages in thread
From: Yu-Chien Peter Lin @ 2023-12-26 7:34 UTC (permalink / raw)
To: Leo Yu-Chi Liang; +Cc: u-boot, randolph
On Tue, Dec 26, 2023 at 02:17:33PM +0800, Leo Yu-Chi Liang wrote:
> Kconfig provides SYS_[I|D]CACHE_OFF config options to switch off caches.
> Provide the corresponding implementation to the options.
>
> Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
> ---
> arch/riscv/cpu/andesv5/cpu.c | 25 ++++++++++++++++---------
> board/AndesTech/ae350/ae350.c | 3 ++-
> 2 files changed, 18 insertions(+), 10 deletions(-)
>
> diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5/cpu.c
> index 63bc24cdfc..e764f6c5c0 100644
> --- a/arch/riscv/cpu/andesv5/cpu.c
> +++ b/arch/riscv/cpu/andesv5/cpu.c
> @@ -32,18 +32,25 @@ void harts_early_init(void)
> if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
> unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
>
> - mcache_ctl_val |= (MCACHE_CTL_DC_COHEN | MCACHE_CTL_IC_EN |
> - MCACHE_CTL_DC_EN | MCACHE_CTL_CCTL_SUEN);
> + mcache_ctl_val |= MCACHE_CTL_CCTL_SUEN;
> +
> + if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF))
> + mcache_ctl_val |= MCACHE_CTL_IC_EN;
> +
> + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
> + mcache_ctl_val |= (MCACHE_CTL_DC_EN | MCACHE_CTL_DC_COHEN);
>
> csr_write(CSR_MCACHE_CTL, mcache_ctl_val);
>
> - /*
> - * Check mcache_ctl.DC_COHEN, we assume this platform does
> - * not support CM if the bit is hard-wired to 0.
> - */
> - if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) {
> - /* Wait for DC_COHSTA bit to be set */
> - while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA));
> + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) {
> + /*
> + * Check mcache_ctl.DC_COHEN, we assume this platform does
> + * not support CM if the bit is hard-wired to 0.
> + */
> + if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) {
> + /* Wait for DC_COHSTA bit to be set */
> + while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA));
> + }
> }
> }
> }
> diff --git a/board/AndesTech/ae350/ae350.c b/board/AndesTech/ae350/ae350.c
> index 772c6bf1ee..bef9e3149e 100644
> --- a/board/AndesTech/ae350/ae350.c
> +++ b/board/AndesTech/ae350/ae350.c
> @@ -102,7 +102,8 @@ void *board_fdt_blob_setup(int *err)
> void spl_board_init()
> {
> /* enable v5l2 cache */
> - enable_caches();
> + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
> + enable_caches();
> }
> #endif
>
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 3/6] andes: cpu: Enable memboost feature
2023-12-26 6:17 [PATCH v2 1/6] andes: csr.h: Clean up CSR definition Leo Yu-Chi Liang
2023-12-26 6:17 ` [PATCH v2 2/6] andes: ae350: Implement cache switch via Kconfig Leo Yu-Chi Liang
@ 2023-12-26 6:17 ` Leo Yu-Chi Liang
2023-12-26 7:42 ` Yu-Chien Peter Lin
2023-12-26 6:17 ` [PATCH v2 4/6] andes: cpu: Enable cache and TLB ECC support Leo Yu-Chi Liang
2023-12-26 7:33 ` [PATCH v2 1/6] andes: csr.h: Clean up CSR definition Yu-Chien Peter Lin
3 siblings, 1 reply; 8+ messages in thread
From: Leo Yu-Chi Liang @ 2023-12-26 6:17 UTC (permalink / raw)
To: u-boot; +Cc: ycliang, randolph, peterlin
Andes CPU has memboost feature including prefetch,
write-around and non-blocking load. Enable them by default.
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
arch/riscv/cpu/andesv5/cpu.c | 9 ++++++++-
arch/riscv/include/asm/arch-andes/csr.h | 6 ++++++
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5/cpu.c
index e764f6c5c0..a23b7948d9 100644
--- a/arch/riscv/cpu/andesv5/cpu.c
+++ b/arch/riscv/cpu/andesv5/cpu.c
@@ -31,8 +31,11 @@ void harts_early_init(void)
/* Enable I/D-cache in SPL */
if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
+ unsigned long mmisc_ctl_val = csr_read(CSR_MMISC_CTL);
- mcache_ctl_val |= MCACHE_CTL_CCTL_SUEN;
+ mcache_ctl_val |= (MCACHE_CTL_CCTL_SUEN | \
+ MCACHE_CTL_IC_PREFETCH_EN | MCACHE_CTL_DC_PREFETCH_EN | \
+ MCACHE_CTL_DC_WAROUND_EN | MCACHE_CTL_L2C_WAROUND_EN);
if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF))
mcache_ctl_val |= MCACHE_CTL_IC_EN;
@@ -52,5 +55,9 @@ void harts_early_init(void)
while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA));
}
}
+
+ mmisc_ctl_val |= MMISC_CTL_NON_BLOCKING_EN;
+
+ csr_write(CSR_MMISC_CTL, mmisc_ctl_val);
}
}
diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h
index 12d5eb6f6c..3f3f05b348 100644
--- a/arch/riscv/include/asm/arch-andes/csr.h
+++ b/arch/riscv/include/asm/arch-andes/csr.h
@@ -19,9 +19,15 @@
#define MCACHE_CTL_IC_EN BIT(0)
#define MCACHE_CTL_DC_EN BIT(1)
#define MCACHE_CTL_CCTL_SUEN BIT(8)
+#define MCACHE_CTL_IC_PREFETCH_EN BIT(9)
+#define MCACHE_CTL_DC_PREFETCH_EN BIT(10)
+#define MCACHE_CTL_DC_WAROUND_EN BIT(13)
+#define MCACHE_CTL_L2C_WAROUND_EN BIT(15)
#define MCACHE_CTL_DC_COHEN BIT(19)
#define MCACHE_CTL_DC_COHSTA BIT(20)
+/* mmisc_ctl register */
+#define MMISC_CTL_NON_BLOCKING_EN BIT(8)
#define CCTL_L1D_WBINVAL_ALL 6
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v2 3/6] andes: cpu: Enable memboost feature
2023-12-26 6:17 ` [PATCH v2 3/6] andes: cpu: Enable memboost feature Leo Yu-Chi Liang
@ 2023-12-26 7:42 ` Yu-Chien Peter Lin
0 siblings, 0 replies; 8+ messages in thread
From: Yu-Chien Peter Lin @ 2023-12-26 7:42 UTC (permalink / raw)
To: Leo Yu-Chi Liang; +Cc: u-boot, randolph
On Tue, Dec 26, 2023 at 02:17:34PM +0800, Leo Yu-Chi Liang wrote:
> Andes CPU has memboost feature including prefetch,
> write-around and non-blocking load. Enable them by default.
>
> Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
> ---
> arch/riscv/cpu/andesv5/cpu.c | 9 ++++++++-
> arch/riscv/include/asm/arch-andes/csr.h | 6 ++++++
> 2 files changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5/cpu.c
> index e764f6c5c0..a23b7948d9 100644
> --- a/arch/riscv/cpu/andesv5/cpu.c
> +++ b/arch/riscv/cpu/andesv5/cpu.c
> @@ -31,8 +31,11 @@ void harts_early_init(void)
> /* Enable I/D-cache in SPL */
> if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
> unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
> + unsigned long mmisc_ctl_val = csr_read(CSR_MMISC_CTL);
>
> - mcache_ctl_val |= MCACHE_CTL_CCTL_SUEN;
> + mcache_ctl_val |= (MCACHE_CTL_CCTL_SUEN | \
> + MCACHE_CTL_IC_PREFETCH_EN | MCACHE_CTL_DC_PREFETCH_EN | \
> + MCACHE_CTL_DC_WAROUND_EN | MCACHE_CTL_L2C_WAROUND_EN);
>
> if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF))
> mcache_ctl_val |= MCACHE_CTL_IC_EN;
> @@ -52,5 +55,9 @@ void harts_early_init(void)
> while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA));
> }
> }
> +
> + mmisc_ctl_val |= MMISC_CTL_NON_BLOCKING_EN;
> +
> + csr_write(CSR_MMISC_CTL, mmisc_ctl_val);
> }
> }
> diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h
> index 12d5eb6f6c..3f3f05b348 100644
> --- a/arch/riscv/include/asm/arch-andes/csr.h
> +++ b/arch/riscv/include/asm/arch-andes/csr.h
> @@ -19,9 +19,15 @@
> #define MCACHE_CTL_IC_EN BIT(0)
> #define MCACHE_CTL_DC_EN BIT(1)
> #define MCACHE_CTL_CCTL_SUEN BIT(8)
> +#define MCACHE_CTL_IC_PREFETCH_EN BIT(9)
> +#define MCACHE_CTL_DC_PREFETCH_EN BIT(10)
> +#define MCACHE_CTL_DC_WAROUND_EN BIT(13)
> +#define MCACHE_CTL_L2C_WAROUND_EN BIT(15)
> #define MCACHE_CTL_DC_COHEN BIT(19)
> #define MCACHE_CTL_DC_COHSTA BIT(20)
>
> +/* mmisc_ctl register */
> +#define MMISC_CTL_NON_BLOCKING_EN BIT(8)
>
> #define CCTL_L1D_WBINVAL_ALL 6
>
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 4/6] andes: cpu: Enable cache and TLB ECC support
2023-12-26 6:17 [PATCH v2 1/6] andes: csr.h: Clean up CSR definition Leo Yu-Chi Liang
2023-12-26 6:17 ` [PATCH v2 2/6] andes: ae350: Implement cache switch via Kconfig Leo Yu-Chi Liang
2023-12-26 6:17 ` [PATCH v2 3/6] andes: cpu: Enable memboost feature Leo Yu-Chi Liang
@ 2023-12-26 6:17 ` Leo Yu-Chi Liang
2023-12-26 7:43 ` Yu-Chien Peter Lin
2023-12-26 7:33 ` [PATCH v2 1/6] andes: csr.h: Clean up CSR definition Yu-Chien Peter Lin
3 siblings, 1 reply; 8+ messages in thread
From: Leo Yu-Chi Liang @ 2023-12-26 6:17 UTC (permalink / raw)
To: u-boot; +Cc: ycliang, randolph, peterlin
Andes CPU supports cache and TLB ECC.
Enable them by default.
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
arch/riscv/cpu/andesv5/cpu.c | 3 ++-
arch/riscv/include/asm/arch-andes/csr.h | 3 +++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5/cpu.c
index a23b7948d9..d25ecba0e8 100644
--- a/arch/riscv/cpu/andesv5/cpu.c
+++ b/arch/riscv/cpu/andesv5/cpu.c
@@ -35,7 +35,8 @@ void harts_early_init(void)
mcache_ctl_val |= (MCACHE_CTL_CCTL_SUEN | \
MCACHE_CTL_IC_PREFETCH_EN | MCACHE_CTL_DC_PREFETCH_EN | \
- MCACHE_CTL_DC_WAROUND_EN | MCACHE_CTL_L2C_WAROUND_EN);
+ MCACHE_CTL_DC_WAROUND_EN | MCACHE_CTL_L2C_WAROUND_EN | \
+ MCACHE_CTL_IC_ECCEN | MCACHE_CTL_DC_ECCEN | MCACHE_CTL_TLB_ECCEN);
if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF))
mcache_ctl_val |= MCACHE_CTL_IC_EN;
diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h
index 3f3f05b348..028fd01c2f 100644
--- a/arch/riscv/include/asm/arch-andes/csr.h
+++ b/arch/riscv/include/asm/arch-andes/csr.h
@@ -18,11 +18,14 @@
#define MCACHE_CTL_IC_EN BIT(0)
#define MCACHE_CTL_DC_EN BIT(1)
+#define MCACHE_CTL_IC_ECCEN BIT(3)
+#define MCACHE_CTL_DC_ECCEN BIT(5)
#define MCACHE_CTL_CCTL_SUEN BIT(8)
#define MCACHE_CTL_IC_PREFETCH_EN BIT(9)
#define MCACHE_CTL_DC_PREFETCH_EN BIT(10)
#define MCACHE_CTL_DC_WAROUND_EN BIT(13)
#define MCACHE_CTL_L2C_WAROUND_EN BIT(15)
+#define MCACHE_CTL_TLB_ECCEN BIT(18)
#define MCACHE_CTL_DC_COHEN BIT(19)
#define MCACHE_CTL_DC_COHSTA BIT(20)
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2 4/6] andes: cpu: Enable cache and TLB ECC support
2023-12-26 6:17 ` [PATCH v2 4/6] andes: cpu: Enable cache and TLB ECC support Leo Yu-Chi Liang
@ 2023-12-26 7:43 ` Yu-Chien Peter Lin
0 siblings, 0 replies; 8+ messages in thread
From: Yu-Chien Peter Lin @ 2023-12-26 7:43 UTC (permalink / raw)
To: Leo Yu-Chi Liang; +Cc: u-boot, randolph
On Tue, Dec 26, 2023 at 02:17:35PM +0800, Leo Yu-Chi Liang wrote:
> Andes CPU supports cache and TLB ECC.
> Enable them by default.
>
> Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
> ---
> arch/riscv/cpu/andesv5/cpu.c | 3 ++-
> arch/riscv/include/asm/arch-andes/csr.h | 3 +++
> 2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5/cpu.c
> index a23b7948d9..d25ecba0e8 100644
> --- a/arch/riscv/cpu/andesv5/cpu.c
> +++ b/arch/riscv/cpu/andesv5/cpu.c
> @@ -35,7 +35,8 @@ void harts_early_init(void)
>
> mcache_ctl_val |= (MCACHE_CTL_CCTL_SUEN | \
> MCACHE_CTL_IC_PREFETCH_EN | MCACHE_CTL_DC_PREFETCH_EN | \
> - MCACHE_CTL_DC_WAROUND_EN | MCACHE_CTL_L2C_WAROUND_EN);
> + MCACHE_CTL_DC_WAROUND_EN | MCACHE_CTL_L2C_WAROUND_EN | \
> + MCACHE_CTL_IC_ECCEN | MCACHE_CTL_DC_ECCEN | MCACHE_CTL_TLB_ECCEN);
>
> if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF))
> mcache_ctl_val |= MCACHE_CTL_IC_EN;
> diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h
> index 3f3f05b348..028fd01c2f 100644
> --- a/arch/riscv/include/asm/arch-andes/csr.h
> +++ b/arch/riscv/include/asm/arch-andes/csr.h
> @@ -18,11 +18,14 @@
>
> #define MCACHE_CTL_IC_EN BIT(0)
> #define MCACHE_CTL_DC_EN BIT(1)
> +#define MCACHE_CTL_IC_ECCEN BIT(3)
> +#define MCACHE_CTL_DC_ECCEN BIT(5)
> #define MCACHE_CTL_CCTL_SUEN BIT(8)
> #define MCACHE_CTL_IC_PREFETCH_EN BIT(9)
> #define MCACHE_CTL_DC_PREFETCH_EN BIT(10)
> #define MCACHE_CTL_DC_WAROUND_EN BIT(13)
> #define MCACHE_CTL_L2C_WAROUND_EN BIT(15)
> +#define MCACHE_CTL_TLB_ECCEN BIT(18)
> #define MCACHE_CTL_DC_COHEN BIT(19)
> #define MCACHE_CTL_DC_COHSTA BIT(20)
>
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 1/6] andes: csr.h: Clean up CSR definition
2023-12-26 6:17 [PATCH v2 1/6] andes: csr.h: Clean up CSR definition Leo Yu-Chi Liang
` (2 preceding siblings ...)
2023-12-26 6:17 ` [PATCH v2 4/6] andes: cpu: Enable cache and TLB ECC support Leo Yu-Chi Liang
@ 2023-12-26 7:33 ` Yu-Chien Peter Lin
3 siblings, 0 replies; 8+ messages in thread
From: Yu-Chien Peter Lin @ 2023-12-26 7:33 UTC (permalink / raw)
To: Leo Yu-Chi Liang; +Cc: u-boot, randolph
On Tue, Dec 26, 2023 at 02:17:32PM +0800, Leo Yu-Chi Liang wrote:
> Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
> arch/riscv/include/asm/arch-andes/csr.h | 20 ++++++++------------
> arch/riscv/include/asm/csr.h | 1 +
> 2 files changed, 9 insertions(+), 12 deletions(-)
>
> diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h
> index 393d51c6dd..12d5eb6f6c 100644
> --- a/arch/riscv/include/asm/arch-andes/csr.h
> +++ b/arch/riscv/include/asm/arch-andes/csr.h
> @@ -12,20 +12,16 @@
>
> #define CSR_MCACHE_CTL 0x7ca
> #define CSR_MMISC_CTL 0x7d0
> -#define CSR_MARCHID 0xf12
> #define CSR_MCCTLCOMMAND 0x7cc
>
> -#define MCACHE_CTL_IC_EN_OFFSET 0
> -#define MCACHE_CTL_DC_EN_OFFSET 1
> -#define MCACHE_CTL_CCTL_SUEN_OFFSET 8
> -#define MCACHE_CTL_DC_COHEN_OFFSET 19
> -#define MCACHE_CTL_DC_COHSTA_OFFSET 20
> -
> -#define MCACHE_CTL_IC_EN BIT(MCACHE_CTL_IC_EN_OFFSET)
> -#define MCACHE_CTL_DC_EN BIT(MCACHE_CTL_DC_EN_OFFSET)
> -#define MCACHE_CTL_CCTL_SUEN BIT(MCACHE_CTL_CCTL_SUEN_OFFSET)
> -#define MCACHE_CTL_DC_COHEN BIT(MCACHE_CTL_DC_COHEN_OFFSET)
> -#define MCACHE_CTL_DC_COHSTA BIT(MCACHE_CTL_DC_COHSTA_OFFSET)
> +/* mcache_ctl register */
> +
> +#define MCACHE_CTL_IC_EN BIT(0)
> +#define MCACHE_CTL_DC_EN BIT(1)
> +#define MCACHE_CTL_CCTL_SUEN BIT(8)
> +#define MCACHE_CTL_DC_COHEN BIT(19)
> +#define MCACHE_CTL_DC_COHSTA BIT(20)
> +
>
> #define CCTL_L1D_WBINVAL_ALL 6
>
> diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
> index 1a15089cae..986f951c31 100644
> --- a/arch/riscv/include/asm/csr.h
> +++ b/arch/riscv/include/asm/csr.h
> @@ -142,6 +142,7 @@
> #define CSR_CYCLEH 0xc80
> #define CSR_TIMEH 0xc81
> #define CSR_INSTRETH 0xc82
> +#define CSR_MARCHID 0xf12
> #define CSR_MHARTID 0xf14
>
> #ifndef __ASSEMBLY__
> --
> 2.34.1
>
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