From: Brian Masney <bmasney@redhat.com>
To: Elliot Berman <quic_eberman@quicinc.com>,
Shazad Hussain <quic_shazhuss@quicinc.com>
Cc: linux-arm-msm@vger.kernel.org,
Bartosz Golaszewski <bartosz.golaszewski@linaro.org>,
Eric Chanudet <echanude@redhat.com>,
Prasad Sodagudi <psodagud@quicinc.com>,
Neil Armstrong <neil.armstrong@linaro.org>
Subject: Re: sa8755p ufs ice bug: gcc_ufs_phy_ice_core_clk status stuck at 'off'
Date: Tue, 9 Jan 2024 16:44:31 -0500 [thread overview]
Message-ID: <ZZ2-P1xzsDwk91Yq@x1> (raw)
In-Reply-To: <d9335515-157b-4b6a-ba41-c31ca76362ee@quicinc.com>
On Mon, Jan 08, 2024 at 03:35:55PM -0800, Elliot Berman wrote:
> On 1/8/2024 12:50 PM, Brian Masney wrote:
> > On Mon, Jan 08, 2024 at 11:44:35PM +0530, Shazad Hussain wrote:
> >> I can see that gcc_ufs_phy_ice_core_clk needs the gcc_ufs_phy_gdsc to be
> >> enabled before this particular clk is enabled. But that required
> >> power-domain I do not see in the ice DT node. That can cause this
> >> problem.
> >
> > Thank you! I'll work on and post a patch set as I find free time over
> > the next week or two.
> I think I observe the same issue on sm8650. Symptoms seem to be same as
> you've described. I'll test out the following diff and see if things
> seem more reliable:
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> index fd4f9dac48a3..c9ea50834dc9 100644
> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> @@ -2526,6 +2526,7 @@ ice: crypto@1d88000 {
> "qcom,inline-crypto-engine";
> reg = <0 0x01d88000 0 0x8000>;
>
> + power-domains = <&gcc UFS_PHY_GDSC>;
> clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
> };
>
>
> If yes, I can post a patch for sm8650 if no else has yet.
The intermittent boot issue is still present against
linux-next-20240109 with the following patch:
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -1556,6 +1556,7 @@ ice: crypto@1d88000 {
compatible = "qcom,sa8775p-inline-crypto-engine",
"qcom,inline-crypto-engine";
reg = <0x0 0x01d88000 0x0 0x8000>;
+ power-domains = <&gcc UFS_PHY_GDSC>;
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
};
Based on digging through the power domain code, I also added
"required-opps = <&rpmhpd_opp_nom>;" to match what the UFS host
controller has, and those tests fail as well.
Shazad: Any other suggestions for other resources that should also be
referenced on the ice node?
Brian
next prev parent reply other threads:[~2024-01-09 21:44 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-04 2:09 sa8755p ufs ice bug: gcc_ufs_phy_ice_core_clk status stuck at 'off' Brian Masney
2024-01-08 18:14 ` Shazad Hussain
2024-01-08 20:50 ` Brian Masney
2024-01-08 23:35 ` Elliot Berman
2024-01-09 21:44 ` Brian Masney [this message]
2024-01-09 21:56 ` Elliot Berman
2024-01-09 23:45 ` Brian Masney
2024-01-15 15:47 ` Brian Masney
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=ZZ2-P1xzsDwk91Yq@x1 \
--to=bmasney@redhat.com \
--cc=bartosz.golaszewski@linaro.org \
--cc=echanude@redhat.com \
--cc=linux-arm-msm@vger.kernel.org \
--cc=neil.armstrong@linaro.org \
--cc=psodagud@quicinc.com \
--cc=quic_eberman@quicinc.com \
--cc=quic_shazhuss@quicinc.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.