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From: Niklas Cassel <cassel@kernel.org>
To: Shawn Lin <shawn.lin@rock-chips.com>
Cc: "Bjorn Helgaas" <bhelgaas@google.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org
Subject: Re: [PATCH v3 1/2] PCI: dw-rockchip: Enable L0S capability
Date: Mon, 14 Apr 2025 16:15:02 +0200	[thread overview]
Message-ID: <Z_0YZnJUiJdffqtA@ryzen> (raw)
In-Reply-To: <1744594051-209255-1-git-send-email-shawn.lin@rock-chips.com>

On Mon, Apr 14, 2025 at 09:27:31AM +0800, Shawn Lin wrote:
> L0S capability isn't enabled on all SoCs by default, so enabling it
> in order to make ASPM L0S work on Rockchip platforms. We have been
> testing it for quite a long time and found the default FTS number
> provided by DWC core doesn't work stable and make LTSSM switch between
> L0S and Recovery, leading to long exit latency, even fail to link sometimes.
> So override it to the max 255 which seems work fine under test for both PHYs
> used by Rockchip platforms.
> 
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

Reviewed-by: Niklas Cassel <cassel@kernel.org>

WARNING: multiple messages have this Message-ID (diff)
From: Niklas Cassel <cassel@kernel.org>
To: Shawn Lin <shawn.lin@rock-chips.com>
Cc: "Bjorn Helgaas" <bhelgaas@google.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org
Subject: Re: [PATCH v3 1/2] PCI: dw-rockchip: Enable L0S capability
Date: Mon, 14 Apr 2025 16:15:02 +0200	[thread overview]
Message-ID: <Z_0YZnJUiJdffqtA@ryzen> (raw)
In-Reply-To: <1744594051-209255-1-git-send-email-shawn.lin@rock-chips.com>

On Mon, Apr 14, 2025 at 09:27:31AM +0800, Shawn Lin wrote:
> L0S capability isn't enabled on all SoCs by default, so enabling it
> in order to make ASPM L0S work on Rockchip platforms. We have been
> testing it for quite a long time and found the default FTS number
> provided by DWC core doesn't work stable and make LTSSM switch between
> L0S and Recovery, leading to long exit latency, even fail to link sometimes.
> So override it to the max 255 which seems work fine under test for both PHYs
> used by Rockchip platforms.
> 
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

Reviewed-by: Niklas Cassel <cassel@kernel.org>

_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

  parent reply	other threads:[~2025-04-14 14:15 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-14  1:27 [PATCH v3 1/2] PCI: dw-rockchip: Enable L0S capability Shawn Lin
2025-04-14  1:27 ` Shawn Lin
2025-04-14  1:28 ` [PATCH v3 2/2] PCI: dw-rockchip: Move rockchip_pcie_ep_hide_broken_ats_cap_rk3588() to .init() Shawn Lin
2025-04-14  1:28   ` Shawn Lin
2025-04-14  1:58   ` Hans Zhang
2025-04-14  1:58     ` Hans Zhang
2025-04-14 14:35   ` Niklas Cassel
2025-04-14 14:35     ` Niklas Cassel
2025-04-14 14:15 ` Niklas Cassel [this message]
2025-04-14 14:15   ` [PATCH v3 1/2] PCI: dw-rockchip: Enable L0S capability Niklas Cassel

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