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From: Marek Marczykowski <marmarek@invisiblethingslab.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: Roger Pau Monne <roger.pau@citrix.com>,
	Andrew Cooper <andrew.cooper3@citrix.com>,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH 2/2] x86/hvm: fix write emulation of RO ranges
Date: Wed, 9 Apr 2025 16:27:40 +0200	[thread overview]
Message-ID: <Z_aD3TsQgrc3_id7@mail-itl> (raw)
In-Reply-To: <16c73cae-2ac0-4811-97d3-b25c95ed5abc@suse.com>

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On Tue, Apr 08, 2025 at 03:57:17PM +0200, Jan Beulich wrote:
> On 08.04.2025 11:31, Roger Pau Monne wrote:
> > When running on AMD hardware in HVM mode the guest linear address (GLA)
> > will not be provided to hvm_emulate_one_mmio(), and instead is
> > unconditionally set of ~0.  As a consequence mmio_ro_emulated_write() will
> > always report an error, as the fault GLA generated by the emulation of the
> > access won't be ~0.
> 
> Which means subpage_mmio_write_accept() is flawed, too, on AMD (or more
> generally whenever .gla_valid isn't set).

That may explain issues I see when using XHCI console on AMD (I can
crash the whole thing using sequence of driver binding/unbinding in
dom0). That's actually the hw12 runner in the other series, but tests
that are included in gitlab do not trigger the issue (fortunately?). But
also, it may be a different issue, as it affects PV dom0 too...

Anyway, I can probably test a patch if subpage_mmio_write_accept() works
as intended (I'll need to check if that path is exercised on AMD too as
it depends on xhci caps layout - it was definitely used on Intel).

-- 
Best Regards,
Marek Marczykowski-Górecki
Invisible Things Lab

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  parent reply	other threads:[~2025-04-09 14:27 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-08  9:31 [PATCH 0/2] x86/hvm: fixes for RO MMIO emulation Roger Pau Monne
2025-04-08  9:31 ` [PATCH 1/2] x86/hvm: remove unreachable MMCFG write emulation Roger Pau Monne
2025-04-08 13:42   ` Jan Beulich
2025-04-08  9:31 ` [PATCH 2/2] x86/hvm: fix write emulation of RO ranges Roger Pau Monne
2025-04-08 13:57   ` Jan Beulich
2025-04-09  9:07     ` Roger Pau Monné
2025-04-09 10:00       ` Jan Beulich
2025-04-09 10:39         ` Roger Pau Monné
2025-04-09 12:59           ` Jan Beulich
2025-04-09 13:33             ` Roger Pau Monné
2025-04-09 13:50               ` Jan Beulich
2025-04-09 14:01                 ` Roger Pau Monné
2025-04-09 14:08                   ` Jan Beulich
2025-04-09 15:33                     ` Roger Pau Monné
2025-04-10  6:27                       ` Jan Beulich
2025-04-10  7:02                         ` Roger Pau Monné
2025-04-09 14:27     ` Marek Marczykowski [this message]
2025-04-08 14:00   ` Andrew Cooper
2025-04-09  9:47     ` Roger Pau Monné

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