From: Niklas Cassel <cassel@kernel.org>
To: Shawn Lin <shawn.lin@rock-chips.com>
Cc: "Bjorn Helgaas" <bhelgaas@google.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org
Subject: Re: [PATCH] PCI: dw-rockchip: Enable L0S capability
Date: Thu, 10 Apr 2025 10:53:53 +0200 [thread overview]
Message-ID: <Z_eHIXpBcnxJP6sa@ryzen> (raw)
In-Reply-To: <1744248981-43371-1-git-send-email-shawn.lin@rock-chips.com>
On Thu, Apr 10, 2025 at 09:36:21AM +0800, Shawn Lin wrote:
> L0S capability isn't enabled on all SoCs by default, so enabling it
> in order to make ASPM L0S work on Rockchip platforms. We have been
> testing it for quite a long time and the default FTS number provided
> by DWC core is broken since it fits only for DWC PHY IP but not for
> other types of PHY IP from other vendors.
I also think it makes sense to split this to two patches.
Modifying N_FTS is completely different from enabling L0S, so please have
a 1/2 patch that overrides N_FTS and a 2/2 patch that enables L0S.
Kind regards,
Niklas
WARNING: multiple messages have this Message-ID (diff)
From: Niklas Cassel <cassel@kernel.org>
To: Shawn Lin <shawn.lin@rock-chips.com>
Cc: "Bjorn Helgaas" <bhelgaas@google.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org
Subject: Re: [PATCH] PCI: dw-rockchip: Enable L0S capability
Date: Thu, 10 Apr 2025 10:53:53 +0200 [thread overview]
Message-ID: <Z_eHIXpBcnxJP6sa@ryzen> (raw)
In-Reply-To: <1744248981-43371-1-git-send-email-shawn.lin@rock-chips.com>
On Thu, Apr 10, 2025 at 09:36:21AM +0800, Shawn Lin wrote:
> L0S capability isn't enabled on all SoCs by default, so enabling it
> in order to make ASPM L0S work on Rockchip platforms. We have been
> testing it for quite a long time and the default FTS number provided
> by DWC core is broken since it fits only for DWC PHY IP but not for
> other types of PHY IP from other vendors.
I also think it makes sense to split this to two patches.
Modifying N_FTS is completely different from enabling L0S, so please have
a 1/2 patch that overrides N_FTS and a 2/2 patch that enables L0S.
Kind regards,
Niklas
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
next prev parent reply other threads:[~2025-04-10 8:53 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-10 1:36 [PATCH] PCI: dw-rockchip: Enable L0S capability Shawn Lin
2025-04-10 1:36 ` Shawn Lin
2025-04-10 8:43 ` Niklas Cassel
2025-04-10 8:43 ` Niklas Cassel
2025-04-10 8:57 ` Shawn Lin
2025-04-10 8:57 ` Shawn Lin
2025-04-10 8:53 ` Niklas Cassel [this message]
2025-04-10 8:53 ` Niklas Cassel
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=Z_eHIXpBcnxJP6sa@ryzen \
--to=cassel@kernel.org \
--cc=bhelgaas@google.com \
--cc=kw@linux.com \
--cc=linux-pci@vger.kernel.org \
--cc=linux-rockchip@lists.infradead.org \
--cc=lpieralisi@kernel.org \
--cc=shawn.lin@rock-chips.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.