Re: [PATCH 2/5] hw/cxl: Update link register definitions.

[fan <nifan.cxl@gmail.com>]

On Wed, Jan 24, 2024 at 01:48:11PM +0000, Jonathan Cameron wrote:
> Not actually implemented, but we need to reserve more space for
> the larger version of the structure in CXL r3.1.
> 
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---

Reviewed-by: Fan Ni <fan.ni@samsung.com>

>  include/hw/cxl/cxl_component.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/include/hw/cxl/cxl_component.h b/include/hw/cxl/cxl_component.h
> index 7d3edef1bf..2c7631bd1e 100644
> --- a/include/hw/cxl/cxl_component.h
> +++ b/include/hw/cxl/cxl_component.h
> @@ -104,10 +104,10 @@ REG32(CXL_RAS_ERR_HEADER0, CXL_RAS_REGISTERS_OFFSET + 0x18)
>      (CXL_RAS_REGISTERS_OFFSET + CXL_RAS_REGISTERS_SIZE)
>  #define CXL_SEC_REGISTERS_SIZE   0 /* We don't implement 1.1 downstream ports */
>  
> -/* 8.2.5.11 - CXL Link Capability Structure */
> +/* CXL r3.1 Section 8.2.4.19: CXL Link Capability Structure */
>  #define CXL_LINK_REGISTERS_OFFSET \
>      (CXL_SEC_REGISTERS_OFFSET + CXL_SEC_REGISTERS_SIZE)
> -#define CXL_LINK_REGISTERS_SIZE   0x38
> +#define CXL_LINK_REGISTERS_SIZE   0x50
>  
>  /* CXL r3.1 Section 8.2.4.20: CXL HDM Decoder Capability Structure */
>  #define HDM_DECODE_MAX 10 /* Maximum decoders for Devices */
> -- 
> 2.39.2
>