Re: [PATCH 3/5] hw/cxl: Update RAS Capability Definitions for version 3.

[fan <nifan.cxl@gmail.com>]

On Wed, Jan 24, 2024 at 01:48:12PM +0000, Jonathan Cameron wrote:
> Part of bringing all of CXL emulation inline with CXL r3.1.
> No functional changes.
> 
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---

Reviewed-by: Fan Ni <fan.ni@samsung.com>

>  include/hw/cxl/cxl_component.h | 5 ++++-
>  hw/cxl/cxl-component-utils.c   | 2 +-
>  2 files changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/include/hw/cxl/cxl_component.h b/include/hw/cxl/cxl_component.h
> index 2c7631bd1e..b5da72b789 100644
> --- a/include/hw/cxl/cxl_component.h
> +++ b/include/hw/cxl/cxl_component.h
> @@ -60,8 +60,9 @@ CXLx_CAPABILITY_HEADER(SNOOP, 0x14)
>   * implements. Some of these are specific to certain types of components, but
>   * this implementation leaves enough space regardless.
>   */
> -/* 8.2.5.9 - CXL RAS Capability Structure */
>  
> +/* CXL r3.1 Section 8.2.4.17: CXL RAS Capability Structure */
> +#define CXL_RAS_CAPABILITY_VERSION 3
>  /* Give ample space for caps before this */
>  #define CXL_RAS_REGISTERS_OFFSET 0x80
>  #define CXL_RAS_REGISTERS_SIZE   0x58
> @@ -95,6 +96,8 @@ REG32(CXL_RAS_COR_ERR_STATUS, CXL_RAS_REGISTERS_OFFSET + 0xc)
>  REG32(CXL_RAS_COR_ERR_MASK, CXL_RAS_REGISTERS_OFFSET + 0x10)
>  REG32(CXL_RAS_ERR_CAP_CTRL, CXL_RAS_REGISTERS_OFFSET + 0x14)
>      FIELD(CXL_RAS_ERR_CAP_CTRL, FIRST_ERROR_POINTER, 0, 6)
> +    FIELD(CXL_RAS_ERR_CAP_CTRL, MULTIPLE_HEADER_RECORDING_CAP, 9, 1)
> +    FIELD(CXL_RAS_ERR_POISON_ENABLED, POISON_ENABLED, 13, 1)
>  REG32(CXL_RAS_ERR_HEADER0, CXL_RAS_REGISTERS_OFFSET + 0x18)
>  #define CXL_RAS_ERR_HEADER_NUM 32
>  /* Offset 0x18 - 0x58 reserved for RAS logs */
> diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c
> index a55cf5a036..848bfa20f1 100644
> --- a/hw/cxl/cxl-component-utils.c
> +++ b/hw/cxl/cxl-component-utils.c
> @@ -325,7 +325,7 @@ void cxl_component_register_init_common(uint32_t *reg_state,
>                         CXL_##reg##_REGISTERS_OFFSET);                         \
>      } while (0)
>  
> -    init_cap_reg(RAS, 2, 2);
> +    init_cap_reg(RAS, 2, CXL_RAS_CAPABILITY_VERSION);
>      ras_init_common(reg_state, write_msk);
>  
>      init_cap_reg(LINK, 4, 2);
> -- 
> 2.39.2
>