* [LTP] [RESEND] [PATCH] hugemmap15: Support RISC-V to do __cache_flush.
@ 2024-05-09 9:07 Hui Min Mina Chou via ltp
2024-05-09 9:54 ` Petr Vorel
0 siblings, 1 reply; 3+ messages in thread
From: Hui Min Mina Chou via ltp @ 2024-05-09 9:07 UTC (permalink / raw)
To: ltp; +Cc: Hui Min Mina Chou, tim609, cynthia, az70021
AndesCore CPU test fails due to an illegal instruction at the first
jumpfunc(), caused by executing incorrect instructions after
self-modifying code.
On RISC-V CPUs, a FENCE.i synchronizes instruction and data streams,
ensuring that subsequent instruction fetch on a RISC-V hart will see
any previous data stores already visible to the same RISC-V hart.
Thus, cacheflush() in the test should also use __clear_cache for RISC-V.
In SMP systems, it invokes the kernel syscall riscv_flush_icache to inform
each hart to flush their local i-caches.
Signed-off-by: Hui Min Mina Chou <minachou@andestech.com>
---
testcases/kernel/mem/hugetlb/hugemmap/hugemmap15.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/testcases/kernel/mem/hugetlb/hugemmap/hugemmap15.c b/testcases/kernel/mem/hugetlb/hugemmap/hugemmap15.c
index 4d198407044a..a84ba6476f1e 100644
--- a/testcases/kernel/mem/hugetlb/hugemmap/hugemmap15.c
+++ b/testcases/kernel/mem/hugetlb/hugemmap/hugemmap15.c
@@ -47,7 +47,7 @@ static void cacheflush(void *p)
{
#if defined(__powerpc__)
asm volatile("dcbst 0,%0; sync; icbi 0,%0; isync" : : "r"(p));
-#elif defined(__arm__) || defined(__aarch64__)
+#elif defined(__arm__) || defined(__aarch64__) || defined(__riscv)
__clear_cache(p, p + COPY_SIZE);
#else
(void)p;
--
2.34.1
--
Mailing list info: https://lists.linux.it/listinfo/ltp
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [LTP] [RESEND] [PATCH] hugemmap15: Support RISC-V to do __cache_flush.
2024-05-09 9:07 [LTP] [RESEND] [PATCH] hugemmap15: Support RISC-V to do __cache_flush Hui Min Mina Chou via ltp
@ 2024-05-09 9:54 ` Petr Vorel
2024-05-10 6:37 ` Mina Chou via ltp
0 siblings, 1 reply; 3+ messages in thread
From: Petr Vorel @ 2024-05-09 9:54 UTC (permalink / raw)
To: Hui Min Mina Chou; +Cc: tim609, cynthia, az70021, ltp
Hi Hui,
thanks, merged!
BTW how are the other RISC-V results in syscalls?
Do you run other runtest files?
Kind regards,
Petr
--
Mailing list info: https://lists.linux.it/listinfo/ltp
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [LTP] [RESEND] [PATCH] hugemmap15: Support RISC-V to do __cache_flush.
2024-05-09 9:54 ` Petr Vorel
@ 2024-05-10 6:37 ` Mina Chou via ltp
0 siblings, 0 replies; 3+ messages in thread
From: Mina Chou via ltp @ 2024-05-10 6:37 UTC (permalink / raw)
To: Petr Vorel; +Cc: tim609, cynthia, az70021, ltp
On Thu, May 09, 2024 at 11:54:39AM +0200, Petr Vorel wrote:
> [EXTERNAL MAIL]
>
> Hi Hui,
>
> thanks, merged!
>
> BTW how are the other RISC-V results in syscalls?
> Do you run other runtest files?
>
> Kind regards,
> Petr
Hi Petr,
We ran all the runtest and found an issue with setitimer in syscalls.
we've submitted a patch earlier[1] and is awaiting review ~~~
Another issue is hugemmap24, fails because the mmap address exceeds
TASK_SIZE. The test was designed for powerpc, but 1TB far exceeds
the riscv's TASK_SIZE=256G. The author hinted at a possible redesign[2],
so we're ignoring this issue.
[1]: https://patchwork.ozlabs.org/project/ltp/patch/20240328083344.277502-1-minachou@andestech.com/
[2]: https://patchwork.ozlabs.org/project/ltp/patch/20230427034039.46512-1-liwang@redhat.com/
Thanks,
Mina
--
Mailing list info: https://lists.linux.it/listinfo/ltp
^ permalink raw reply [flat|nested] 3+ messages in thread
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2024-05-09 9:07 [LTP] [RESEND] [PATCH] hugemmap15: Support RISC-V to do __cache_flush Hui Min Mina Chou via ltp
2024-05-09 9:54 ` Petr Vorel
2024-05-10 6:37 ` Mina Chou via ltp
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