[PATCH 00/19] drm/i915/psr: implicit dev_priv removal

[PATCH 00/19] drm/i915/psr: implicit dev_priv removal

[Jani Nikula]

Similar to [1], but for intel_psr_regs.h.

Again, if this is too much, I can squash the patches. But this is
probably easier to review.

BR,
Jani.


[1] https://lore.kernel.org/r/cover.1714399071.git.jani.nikula@intel.com


Jani Nikula (19):
  drm/i915: pass dev_priv explicitly to TRANS_EXITLINE
  drm/i915: pass dev_priv explicitly to EDP_PSR_CTL
  drm/i915: pass dev_priv explicitly to TRANS_PSR_IMR
  drm/i915: pass dev_priv explicitly to TRANS_PSR_IIR
  drm/i915: pass dev_priv explicitly to EDP_PSR_AUX_CTL
  drm/i915: pass dev_priv explicitly to EDP_PSR_AUX_DATA
  drm/i915: pass dev_priv explicitly to EDP_PSR_STATUS
  drm/i915: pass dev_priv explicitly to EDP_PSR_PERF_CNT
  drm/i915: pass dev_priv explicitly to EDP_PSR_DEBUG
  drm/i915: pass dev_priv explicitly to EDP_PSR2_CTL
  drm/i915: pass dev_priv explicitly to PSR_EVENT
  drm/i915: pass dev_priv explicitly to EDP_PSR2_STATUS
  drm/i915: pass dev_priv explicitly to _PSR2_SU_STATUS
  drm/i915: pass dev_priv explicitly to PSR2_MAN_TRK_CTL
  drm/i915: pass dev_priv explicitly to PIPE_SRCSZ_ERLY_TPT
  drm/i915: pass dev_priv explicitly to ALPM_CTL
  drm/i915: pass dev_priv explicitly to ALPM_CTL2
  drm/i915: pass dev_priv explicitly to PORT_ALPM_CTL
  drm/i915: pass dev_priv explicitly to PORT_ALPM_LFPS_CTL

 drivers/gpu/drm/i915/display/intel_cursor.c   |  2 +-
 .../gpu/drm/i915/display/intel_display_irq.c  | 14 ++-
 drivers/gpu/drm/i915/display/intel_psr.c      | 89 +++++++++++--------
 drivers/gpu/drm/i915/display/intel_psr_regs.h | 40 ++++-----
 4 files changed, 85 insertions(+), 60 deletions(-)

-- 
2.39.2

[PATCH 01/19] drm/i915: pass dev_priv explicitly to TRANS_EXITLINE

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_EXITLINE register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c      | 7 +++++--
 drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index f5b33335a9ae..1cbd8c6714b1 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1685,7 +1685,8 @@ void intel_psr_get_config(struct intel_encoder *encoder,
 	}
 
 	if (DISPLAY_VER(dev_priv) >= 12) {
-		val = intel_de_read(dev_priv, TRANS_EXITLINE(cpu_transcoder));
+		val = intel_de_read(dev_priv,
+				    TRANS_EXITLINE(dev_priv, cpu_transcoder));
 		pipe_config->dc3co_exitline = REG_FIELD_GET(EXITLINE_MASK, val);
 	}
 unlock:
@@ -1877,7 +1878,9 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 	 * transcoder, EXITLINE will need to be unset when disabling PSR
 	 */
 	if (intel_dp->psr.dc3co_exitline)
-		intel_de_rmw(dev_priv, TRANS_EXITLINE(cpu_transcoder), EXITLINE_MASK,
+		intel_de_rmw(dev_priv,
+			     TRANS_EXITLINE(dev_priv, cpu_transcoder),
+			     EXITLINE_MASK,
 			     intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT | EXITLINE_ENABLE);
 
 	if (HAS_PSR_HW_TRACKING(dev_priv) && HAS_PSR2_SEL_FETCH(dev_priv))
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index ebc22999572c..0e0c71ea9fe3 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -9,7 +9,7 @@
 #include "intel_display_reg_defs.h"
 #include "intel_dp_aux_regs.h"
 
-#define TRANS_EXITLINE(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_EXITLINE_A)
+#define TRANS_EXITLINE(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_EXITLINE_A)
 #define   EXITLINE_ENABLE	REG_BIT(31)
 #define   EXITLINE_MASK		REG_GENMASK(12, 0)
 #define   EXITLINE_SHIFT	0
-- 
2.39.2

[PATCH 02/19] drm/i915: pass dev_priv explicitly to EDP_PSR_CTL

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the EDP_PSR_CTL register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c      | 2 +-
 drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 1cbd8c6714b1..57414a1375b1 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -269,7 +269,7 @@ static i915_reg_t psr_ctl_reg(struct drm_i915_private *dev_priv,
 			      enum transcoder cpu_transcoder)
 {
 	if (DISPLAY_VER(dev_priv) >= 8)
-		return EDP_PSR_CTL(cpu_transcoder);
+		return EDP_PSR_CTL(dev_priv, cpu_transcoder);
 	else
 		return HSW_SRD_CTL;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index 0e0c71ea9fe3..d815f08aac2c 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -23,7 +23,7 @@
 #define HSW_SRD_CTL				_MMIO(0x64800)
 #define _SRD_CTL_A				0x60800
 #define _SRD_CTL_EDP				0x6f800
-#define EDP_PSR_CTL(tran)			_MMIO_TRANS2(dev_priv, tran, _SRD_CTL_A)
+#define EDP_PSR_CTL(dev_priv, tran)			_MMIO_TRANS2(dev_priv, tran, _SRD_CTL_A)
 #define   EDP_PSR_ENABLE			REG_BIT(31)
 #define   BDW_PSR_SINGLE_FRAME			REG_BIT(30)
 #define   EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK	REG_BIT(29) /* SW can't modify */
-- 
2.39.2

[PATCH 03/19] drm/i915: pass dev_priv explicitly to TRANS_PSR_IMR

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_PSR_IMR register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_irq.c | 4 +++-
 drivers/gpu/drm/i915/display/intel_psr.c         | 2 +-
 drivers/gpu/drm/i915/display/intel_psr_regs.h    | 2 +-
 3 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index c337e0597541..a9bcf249e925 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -1455,7 +1455,9 @@ void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
 			if (!intel_display_power_is_enabled(dev_priv, domain))
 				continue;
 
-			intel_uncore_write(uncore, TRANS_PSR_IMR(trans), 0xffffffff);
+			intel_uncore_write(uncore,
+				           TRANS_PSR_IMR(dev_priv, trans),
+				           0xffffffff);
 			intel_uncore_write(uncore, TRANS_PSR_IIR(trans), 0xffffffff);
 		}
 	} else {
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 57414a1375b1..12b541e8bbf9 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -305,7 +305,7 @@ static i915_reg_t psr_imr_reg(struct drm_i915_private *dev_priv,
 			      enum transcoder cpu_transcoder)
 {
 	if (DISPLAY_VER(dev_priv) >= 12)
-		return TRANS_PSR_IMR(cpu_transcoder);
+		return TRANS_PSR_IMR(dev_priv, cpu_transcoder);
 	else
 		return EDP_PSR_IMR;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index d815f08aac2c..40dc6ee7ec1d 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -66,7 +66,7 @@
 #define EDP_PSR_IIR				_MMIO(0x64838)
 #define _PSR_IMR_A				0x60814
 #define _PSR_IIR_A				0x60818
-#define TRANS_PSR_IMR(tran)			_MMIO_TRANS2(dev_priv, tran, _PSR_IMR_A)
+#define TRANS_PSR_IMR(dev_priv, tran)			_MMIO_TRANS2(dev_priv, tran, _PSR_IMR_A)
 #define TRANS_PSR_IIR(tran)			_MMIO_TRANS2(dev_priv, tran, _PSR_IIR_A)
 #define   _EDP_PSR_TRANS_SHIFT(trans)		((trans) == TRANSCODER_EDP ? \
 						 0 : ((trans) - TRANSCODER_A + 1) * 8)
-- 
2.39.2

[PATCH 04/19] drm/i915: pass dev_priv explicitly to TRANS_PSR_IIR

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_PSR_IIR register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_irq.c | 10 +++++++---
 drivers/gpu/drm/i915/display/intel_psr.c         |  2 +-
 drivers/gpu/drm/i915/display/intel_psr_regs.h    |  2 +-
 3 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index a9bcf249e925..c41f058acaff 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -876,7 +876,8 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
 			struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
 			if (DISPLAY_VER(dev_priv) >= 12)
-				iir_reg = TRANS_PSR_IIR(intel_dp->psr.transcoder);
+				iir_reg = TRANS_PSR_IIR(dev_priv,
+						        intel_dp->psr.transcoder);
 			else
 				iir_reg = EDP_PSR_IIR;
 
@@ -1458,7 +1459,9 @@ void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
 			intel_uncore_write(uncore,
 				           TRANS_PSR_IMR(dev_priv, trans),
 				           0xffffffff);
-			intel_uncore_write(uncore, TRANS_PSR_IIR(trans), 0xffffffff);
+			intel_uncore_write(uncore,
+				           TRANS_PSR_IIR(dev_priv, trans),
+				           0xffffffff);
 		}
 	} else {
 		intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
@@ -1690,7 +1693,8 @@ void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 			if (!intel_display_power_is_enabled(dev_priv, domain))
 				continue;
 
-			gen3_assert_iir_is_zero(uncore, TRANS_PSR_IIR(trans));
+			gen3_assert_iir_is_zero(uncore,
+						TRANS_PSR_IIR(dev_priv, trans));
 		}
 	} else {
 		gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 12b541e8bbf9..0b1f7e62470e 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -314,7 +314,7 @@ static i915_reg_t psr_iir_reg(struct drm_i915_private *dev_priv,
 			      enum transcoder cpu_transcoder)
 {
 	if (DISPLAY_VER(dev_priv) >= 12)
-		return TRANS_PSR_IIR(cpu_transcoder);
+		return TRANS_PSR_IIR(dev_priv, cpu_transcoder);
 	else
 		return EDP_PSR_IIR;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index 40dc6ee7ec1d..5fd4f875ade0 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -67,7 +67,7 @@
 #define _PSR_IMR_A				0x60814
 #define _PSR_IIR_A				0x60818
 #define TRANS_PSR_IMR(dev_priv, tran)			_MMIO_TRANS2(dev_priv, tran, _PSR_IMR_A)
-#define TRANS_PSR_IIR(tran)			_MMIO_TRANS2(dev_priv, tran, _PSR_IIR_A)
+#define TRANS_PSR_IIR(dev_priv, tran)			_MMIO_TRANS2(dev_priv, tran, _PSR_IIR_A)
 #define   _EDP_PSR_TRANS_SHIFT(trans)		((trans) == TRANSCODER_EDP ? \
 						 0 : ((trans) - TRANSCODER_A + 1) * 8)
 #define   TGL_PSR_MASK			REG_GENMASK(2, 0)
-- 
2.39.2

[PATCH 05/19] drm/i915: pass dev_priv explicitly to EDP_PSR_AUX_CTL

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the EDP_PSR_AUX_CTL register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c      | 2 +-
 drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 0b1f7e62470e..daeb1b65a2e5 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -323,7 +323,7 @@ static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv,
 				  enum transcoder cpu_transcoder)
 {
 	if (DISPLAY_VER(dev_priv) >= 8)
-		return EDP_PSR_AUX_CTL(cpu_transcoder);
+		return EDP_PSR_AUX_CTL(dev_priv, cpu_transcoder);
 	else
 		return HSW_SRD_AUX_CTL;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index 5fd4f875ade0..a4f785bcf605 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -86,7 +86,7 @@
 #define HSW_SRD_AUX_CTL				_MMIO(0x64810)
 #define _SRD_AUX_CTL_A				0x60810
 #define _SRD_AUX_CTL_EDP			0x6f810
-#define EDP_PSR_AUX_CTL(tran)			_MMIO_TRANS2(dev_priv, tran, _SRD_AUX_CTL_A)
+#define EDP_PSR_AUX_CTL(dev_priv, tran)			_MMIO_TRANS2(dev_priv, tran, _SRD_AUX_CTL_A)
 #define   EDP_PSR_AUX_CTL_TIME_OUT_MASK		DP_AUX_CH_CTL_TIME_OUT_MASK
 #define   EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK	DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
 #define   EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK	DP_AUX_CH_CTL_PRECHARGE_2US_MASK
-- 
2.39.2

[PATCH 06/19] drm/i915: pass dev_priv explicitly to EDP_PSR_AUX_DATA

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the EDP_PSR_AUX_DATA register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c      | 2 +-
 drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index daeb1b65a2e5..5fe9feddc0e0 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -332,7 +332,7 @@ static i915_reg_t psr_aux_data_reg(struct drm_i915_private *dev_priv,
 				   enum transcoder cpu_transcoder, int i)
 {
 	if (DISPLAY_VER(dev_priv) >= 8)
-		return EDP_PSR_AUX_DATA(cpu_transcoder, i);
+		return EDP_PSR_AUX_DATA(dev_priv, cpu_transcoder, i);
 	else
 		return HSW_SRD_AUX_DATA(i);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index a4f785bcf605..6a6d7de901bc 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -96,7 +96,7 @@
 #define HSW_SRD_AUX_DATA(i)			_MMIO(0x64814 + (i) * 4) /* 5 registers */
 #define _SRD_AUX_DATA_A				0x60814
 #define _SRD_AUX_DATA_EDP			0x6f814
-#define EDP_PSR_AUX_DATA(tran, i)		_MMIO_TRANS2(dev_priv, tran, _SRD_AUX_DATA_A + (i) * 4) /* 5 registers */
+#define EDP_PSR_AUX_DATA(dev_priv, tran, i)		_MMIO_TRANS2(dev_priv, tran, _SRD_AUX_DATA_A + (i) * 4) /* 5 registers */
 
 #define HSW_SRD_STATUS				_MMIO(0x64840)
 #define _SRD_STATUS_A				0x60840
-- 
2.39.2

[PATCH 07/19] drm/i915: pass dev_priv explicitly to EDP_PSR_STATUS

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the EDP_PSR_STATUS register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c      | 2 +-
 drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 5fe9feddc0e0..1a52a69e1906 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -296,7 +296,7 @@ static i915_reg_t psr_status_reg(struct drm_i915_private *dev_priv,
 				 enum transcoder cpu_transcoder)
 {
 	if (DISPLAY_VER(dev_priv) >= 8)
-		return EDP_PSR_STATUS(cpu_transcoder);
+		return EDP_PSR_STATUS(dev_priv, cpu_transcoder);
 	else
 		return HSW_SRD_STATUS;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index 6a6d7de901bc..4f3e58076a48 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -101,7 +101,7 @@
 #define HSW_SRD_STATUS				_MMIO(0x64840)
 #define _SRD_STATUS_A				0x60840
 #define _SRD_STATUS_EDP				0x6f840
-#define EDP_PSR_STATUS(tran)			_MMIO_TRANS2(dev_priv, tran, _SRD_STATUS_A)
+#define EDP_PSR_STATUS(dev_priv, tran)			_MMIO_TRANS2(dev_priv, tran, _SRD_STATUS_A)
 #define   EDP_PSR_STATUS_STATE_MASK		REG_GENMASK(31, 29)
 #define   EDP_PSR_STATUS_STATE_IDLE		REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 0)
 #define   EDP_PSR_STATUS_STATE_SRDONACK		REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 1)
-- 
2.39.2

[PATCH 08/19] drm/i915: pass dev_priv explicitly to EDP_PSR_PERF_CNT

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the EDP_PSR_PERF_CNT register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c      | 2 +-
 drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 1a52a69e1906..162dd07c243f 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -287,7 +287,7 @@ static i915_reg_t psr_perf_cnt_reg(struct drm_i915_private *dev_priv,
 				   enum transcoder cpu_transcoder)
 {
 	if (DISPLAY_VER(dev_priv) >= 8)
-		return EDP_PSR_PERF_CNT(cpu_transcoder);
+		return EDP_PSR_PERF_CNT(dev_priv, cpu_transcoder);
 	else
 		return HSW_SRD_PERF_CNT;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index 4f3e58076a48..ef7f32c98d55 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -126,7 +126,7 @@
 #define HSW_SRD_PERF_CNT		_MMIO(0x64844)
 #define _SRD_PERF_CNT_A			0x60844
 #define _SRD_PERF_CNT_EDP		0x6f844
-#define EDP_PSR_PERF_CNT(tran)		_MMIO_TRANS2(dev_priv, tran, _SRD_PERF_CNT_A)
+#define EDP_PSR_PERF_CNT(dev_priv, tran)		_MMIO_TRANS2(dev_priv, tran, _SRD_PERF_CNT_A)
 #define   EDP_PSR_PERF_CNT_MASK		REG_GENMASK(23, 0)
 
 /* PSR_MASK on SKL+ */
-- 
2.39.2

[PATCH 09/19] drm/i915: pass dev_priv explicitly to EDP_PSR_DEBUG

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the EDP_PSR_DEBUG register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c      | 2 +-
 drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 162dd07c243f..fa1fd04d3b4a 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -278,7 +278,7 @@ static i915_reg_t psr_debug_reg(struct drm_i915_private *dev_priv,
 				enum transcoder cpu_transcoder)
 {
 	if (DISPLAY_VER(dev_priv) >= 8)
-		return EDP_PSR_DEBUG(cpu_transcoder);
+		return EDP_PSR_DEBUG(dev_priv, cpu_transcoder);
 	else
 		return HSW_SRD_DEBUG;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index ef7f32c98d55..a74705aedbb5 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -133,7 +133,7 @@
 #define HSW_SRD_DEBUG				_MMIO(0x64860)
 #define _SRD_DEBUG_A				0x60860
 #define _SRD_DEBUG_EDP				0x6f860
-#define EDP_PSR_DEBUG(tran)			_MMIO_TRANS2(dev_priv, tran, _SRD_DEBUG_A)
+#define EDP_PSR_DEBUG(dev_priv, tran)			_MMIO_TRANS2(dev_priv, tran, _SRD_DEBUG_A)
 #define   EDP_PSR_DEBUG_MASK_MAX_SLEEP		REG_BIT(28)
 #define   EDP_PSR_DEBUG_MASK_LPSP		REG_BIT(27)
 #define   EDP_PSR_DEBUG_MASK_MEMUP		REG_BIT(26)
-- 
2.39.2

[PATCH 10/19] drm/i915: pass dev_priv explicitly to EDP_PSR2_CTL

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the EDP_PSR2_CTL register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c      | 15 +++++++++------
 drivers/gpu/drm/i915/display/intel_psr_regs.h |  2 +-
 2 files changed, 10 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index fa1fd04d3b4a..156660ab7adf 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -932,7 +932,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 	 */
 	intel_de_write(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder), psr_val);
 
-	intel_de_write(dev_priv, EDP_PSR2_CTL(cpu_transcoder), val);
+	intel_de_write(dev_priv, EDP_PSR2_CTL(dev_priv, cpu_transcoder), val);
 }
 
 static bool
@@ -963,7 +963,7 @@ static void psr2_program_idle_frames(struct intel_dp *intel_dp,
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
 
-	intel_de_rmw(dev_priv, EDP_PSR2_CTL(cpu_transcoder),
+	intel_de_rmw(dev_priv, EDP_PSR2_CTL(dev_priv, cpu_transcoder),
 		     EDP_PSR2_IDLE_FRAMES_MASK,
 		     EDP_PSR2_IDLE_FRAMES(idle_frames));
 }
@@ -1700,7 +1700,7 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
 
 	drm_WARN_ON(&dev_priv->drm,
 		    transcoder_has_psr2(dev_priv, cpu_transcoder) &&
-		    intel_de_read(dev_priv, EDP_PSR2_CTL(cpu_transcoder)) & EDP_PSR2_ENABLE);
+		    intel_de_read(dev_priv, EDP_PSR2_CTL(dev_priv, cpu_transcoder)) & EDP_PSR2_ENABLE);
 
 	drm_WARN_ON(&dev_priv->drm,
 		    intel_de_read(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder)) & EDP_PSR_ENABLE);
@@ -2011,7 +2011,8 @@ static void intel_psr_exit(struct intel_dp *intel_dp)
 
 	if (!intel_dp->psr.active) {
 		if (transcoder_has_psr2(dev_priv, cpu_transcoder)) {
-			val = intel_de_read(dev_priv, EDP_PSR2_CTL(cpu_transcoder));
+			val = intel_de_read(dev_priv,
+					    EDP_PSR2_CTL(dev_priv, cpu_transcoder));
 			drm_WARN_ON(&dev_priv->drm, val & EDP_PSR2_ENABLE);
 		}
 
@@ -2027,7 +2028,8 @@ static void intel_psr_exit(struct intel_dp *intel_dp)
 	} else if (intel_dp->psr.psr2_enabled) {
 		tgl_disallow_dc3co_on_psr2_exit(intel_dp);
 
-		val = intel_de_rmw(dev_priv, EDP_PSR2_CTL(cpu_transcoder),
+		val = intel_de_rmw(dev_priv,
+				   EDP_PSR2_CTL(dev_priv, cpu_transcoder),
 				   EDP_PSR2_ENABLE, 0);
 
 		drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR2_ENABLE));
@@ -3529,7 +3531,8 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
 		val = intel_de_read(dev_priv, TRANS_DP2_CTL(cpu_transcoder));
 		enabled = val & TRANS_DP2_PANEL_REPLAY_ENABLE;
 	} else if (psr->psr2_enabled) {
-		val = intel_de_read(dev_priv, EDP_PSR2_CTL(cpu_transcoder));
+		val = intel_de_read(dev_priv,
+				    EDP_PSR2_CTL(dev_priv, cpu_transcoder));
 		enabled = val & EDP_PSR2_ENABLE;
 	} else {
 		val = intel_de_read(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder));
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index a74705aedbb5..785e4f9e7828 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -153,7 +153,7 @@
 
 #define _PSR2_CTL_A				0x60900
 #define _PSR2_CTL_EDP				0x6f900
-#define EDP_PSR2_CTL(tran)			_MMIO_TRANS2(dev_priv, tran, _PSR2_CTL_A)
+#define EDP_PSR2_CTL(dev_priv, tran)			_MMIO_TRANS2(dev_priv, tran, _PSR2_CTL_A)
 #define   EDP_PSR2_ENABLE			REG_BIT(31)
 #define   EDP_SU_TRACK_ENABLE			REG_BIT(30) /* up to adl-p */
 #define   TGL_EDP_PSR2_BLOCK_COUNT_MASK		REG_BIT(28)
-- 
2.39.2

[PATCH 11/19] drm/i915: pass dev_priv explicitly to PSR_EVENT

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PSR_EVENT register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c      | 4 +++-
 drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 156660ab7adf..2dca9957a06b 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -415,7 +415,9 @@ void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir)
 		if (DISPLAY_VER(dev_priv) >= 9) {
 			u32 val;
 
-			val = intel_de_rmw(dev_priv, PSR_EVENT(cpu_transcoder), 0, 0);
+			val = intel_de_rmw(dev_priv,
+					   PSR_EVENT(dev_priv, cpu_transcoder),
+					   0, 0);
 
 			psr_event_print(dev_priv, val, intel_dp->psr.psr2_enabled);
 		}
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index 785e4f9e7828..817bc372bf35 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -195,7 +195,7 @@
 #define _PSR_EVENT_TRANS_C			0x62848
 #define _PSR_EVENT_TRANS_D			0x63848
 #define _PSR_EVENT_TRANS_EDP			0x6f848
-#define PSR_EVENT(tran)				_MMIO_TRANS2(dev_priv, tran, _PSR_EVENT_TRANS_A)
+#define PSR_EVENT(dev_priv, tran)				_MMIO_TRANS2(dev_priv, tran, _PSR_EVENT_TRANS_A)
 #define  PSR_EVENT_PSR2_WD_TIMER_EXPIRE		REG_BIT(17)
 #define  PSR_EVENT_PSR2_DISABLED		REG_BIT(16)
 #define  PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN	REG_BIT(15)
-- 
2.39.2

[PATCH 12/19] drm/i915: pass dev_priv explicitly to EDP_PSR2_STATUS

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the EDP_PSR2_STATUS register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c      | 9 +++++----
 drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 2dca9957a06b..36c08cd3a624 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2052,7 +2052,7 @@ static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp)
 	u32 psr_status_mask;
 
 	if (intel_dp->psr.psr2_enabled) {
-		psr_status = EDP_PSR2_STATUS(cpu_transcoder);
+		psr_status = EDP_PSR2_STATUS(dev_priv, cpu_transcoder);
 		psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
 	} else {
 		psr_status = psr_status_reg(dev_priv, cpu_transcoder);
@@ -2768,7 +2768,7 @@ static int _psr2_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
 	 * EDP_PSR2_STATUS_STATE_DEEP_SLEEP to be cleared.
 	 */
 	return intel_de_wait_for_clear(dev_priv,
-				       EDP_PSR2_STATUS(cpu_transcoder),
+				       EDP_PSR2_STATUS(dev_priv, cpu_transcoder),
 				       EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 50);
 }
 
@@ -2835,7 +2835,7 @@ static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp)
 		return false;
 
 	if (intel_dp->psr.psr2_enabled) {
-		reg = EDP_PSR2_STATUS(cpu_transcoder);
+		reg = EDP_PSR2_STATUS(dev_priv, cpu_transcoder);
 		mask = EDP_PSR2_STATUS_STATE_MASK;
 	} else {
 		reg = psr_status_reg(dev_priv, cpu_transcoder);
@@ -3467,7 +3467,8 @@ psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
 			"BUF_ON",
 			"TG_ON"
 		};
-		val = intel_de_read(dev_priv, EDP_PSR2_STATUS(cpu_transcoder));
+		val = intel_de_read(dev_priv,
+				    EDP_PSR2_STATUS(dev_priv, cpu_transcoder));
 		status_val = REG_FIELD_GET(EDP_PSR2_STATUS_STATE_MASK, val);
 		if (status_val < ARRAY_SIZE(live_status))
 			status = live_status[status_val];
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index 817bc372bf35..e6c62512512f 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -215,7 +215,7 @@
 
 #define _PSR2_STATUS_A				0x60940
 #define _PSR2_STATUS_EDP			0x6f940
-#define EDP_PSR2_STATUS(tran)			_MMIO_TRANS2(dev_priv, tran, _PSR2_STATUS_A)
+#define EDP_PSR2_STATUS(dev_priv, tran)			_MMIO_TRANS2(dev_priv, tran, _PSR2_STATUS_A)
 #define EDP_PSR2_STATUS_STATE_MASK		REG_GENMASK(31, 28)
 #define EDP_PSR2_STATUS_STATE_DEEP_SLEEP	REG_FIELD_PREP(EDP_PSR2_STATUS_STATE_MASK, 0x8)
 
-- 
2.39.2

[PATCH 13/19] drm/i915: pass dev_priv explicitly to _PSR2_SU_STATUS

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the _PSR2_SU_STATUS register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr_regs.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index e6c62512512f..762fc0ad7eb5 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -221,8 +221,8 @@
 
 #define _PSR2_SU_STATUS_A		0x60914
 #define _PSR2_SU_STATUS_EDP		0x6f914
-#define _PSR2_SU_STATUS(tran, index)	_MMIO_TRANS2(dev_priv, tran, _PSR2_SU_STATUS_A + (index) * 4)
-#define PSR2_SU_STATUS(tran, frame)	(_PSR2_SU_STATUS(tran, (frame) / 3))
+#define _PSR2_SU_STATUS(dev_priv, tran, index)	_MMIO_TRANS2(dev_priv, tran, _PSR2_SU_STATUS_A + (index) * 4)
+#define PSR2_SU_STATUS(tran, frame)	(_PSR2_SU_STATUS(dev_priv, tran, (frame) / 3))
 #define PSR2_SU_STATUS_SHIFT(frame)	(((frame) % 3) * 10)
 #define PSR2_SU_STATUS_MASK(frame)	(0x3ff << PSR2_SU_STATUS_SHIFT(frame))
 #define PSR2_SU_STATUS_FRAMES		8
-- 
2.39.2

[PATCH 14/19] drm/i915: pass dev_priv explicitly to PSR2_MAN_TRK_CTL

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PSR2_MAN_TRK_CTL register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c      | 23 ++++++++++++-------
 drivers/gpu/drm/i915/display/intel_psr_regs.h |  2 +-
 2 files changed, 16 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 36c08cd3a624..ded7795e4c3a 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -844,7 +844,8 @@ static void dg2_activate_panel_replay(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 
-	intel_de_rmw(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
+	intel_de_rmw(dev_priv,
+		     PSR2_MAN_TRK_CTL(dev_priv, intel_dp->psr.transcoder),
 		     0, ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME);
 
 	intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,
@@ -919,10 +920,12 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 	if (intel_dp->psr.psr2_sel_fetch_enabled) {
 		u32 tmp;
 
-		tmp = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(cpu_transcoder));
+		tmp = intel_de_read(dev_priv,
+				    PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder));
 		drm_WARN_ON(&dev_priv->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE));
 	} else if (HAS_PSR2_SEL_FETCH(dev_priv)) {
-		intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(cpu_transcoder), 0);
+		intel_de_write(dev_priv,
+			       PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder), 0);
 	}
 
 	if (psr2_su_region_et_valid(intel_dp))
@@ -1681,7 +1684,8 @@ void intel_psr_get_config(struct intel_encoder *encoder,
 		goto unlock;
 
 	if (HAS_PSR2_SEL_FETCH(dev_priv)) {
-		val = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(cpu_transcoder));
+		val = intel_de_read(dev_priv,
+				    PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder));
 		if (val & PSR2_MAN_TRK_CTL_ENABLE)
 			pipe_config->enable_psr2_sel_fetch = true;
 	}
@@ -2251,7 +2255,7 @@ static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
 
 	if (intel_dp->psr.psr2_sel_fetch_enabled)
 		intel_de_write(dev_priv,
-			       PSR2_MAN_TRK_CTL(cpu_transcoder),
+			       PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder),
 			       man_trk_ctl_enable_bit_get(dev_priv) |
 			       man_trk_ctl_partial_frame_bit_get(dev_priv) |
 			       man_trk_ctl_single_full_frame_bit_get(dev_priv) |
@@ -2293,7 +2297,7 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st
 		break;
 	}
 
-	intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(cpu_transcoder),
+	intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder),
 		       crtc_state->psr2_man_track_ctl);
 
 	if (!crtc_state->enable_psr2_su_region_et)
@@ -3014,7 +3018,9 @@ static void _psr_invalidate_handle(struct intel_dp *intel_dp)
 		val = man_trk_ctl_enable_bit_get(dev_priv) |
 		      man_trk_ctl_partial_frame_bit_get(dev_priv) |
 		      man_trk_ctl_continuos_full_frame(dev_priv);
-		intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(cpu_transcoder), val);
+		intel_de_write(dev_priv,
+			       PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder),
+			       val);
 		intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
 		intel_dp->psr.psr2_sel_fetch_cff_enabled = true;
 	} else {
@@ -3112,7 +3118,8 @@ static void _psr_flush_handle(struct intel_dp *intel_dp)
 				 * SU configuration in case update is sent for any reason after
 				 * sff bit gets cleared by the HW on next vblank.
 				 */
-				intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(cpu_transcoder),
+				intel_de_write(dev_priv,
+					       PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder),
 					       val);
 				intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
 				intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index 762fc0ad7eb5..55e07e87dfbd 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -229,7 +229,7 @@
 
 #define _PSR2_MAN_TRK_CTL_A					0x60910
 #define _PSR2_MAN_TRK_CTL_EDP					0x6f910
-#define PSR2_MAN_TRK_CTL(tran)					_MMIO_TRANS2(dev_priv, tran, _PSR2_MAN_TRK_CTL_A)
+#define PSR2_MAN_TRK_CTL(dev_priv, tran)					_MMIO_TRANS2(dev_priv, tran, _PSR2_MAN_TRK_CTL_A)
 #define  PSR2_MAN_TRK_CTL_ENABLE				REG_BIT(31)
 #define  PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK		REG_GENMASK(30, 21)
 #define  PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)		REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
-- 
2.39.2

[PATCH 15/19] drm/i915: pass dev_priv explicitly to PIPE_SRCSZ_ERLY_TPT

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_SRCSZ_ERLY_TPT register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cursor.c   | 2 +-
 drivers/gpu/drm/i915/display/intel_psr.c      | 2 +-
 drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
index 23a122ee20c9..2118b87ccb10 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -523,7 +523,7 @@ static void wa_16021440873(struct intel_plane *plane,
 
 	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), ctl);
 
-	intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(pipe),
+	intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(dev_priv, pipe),
 		       PIPESRC_HEIGHT(et_y_position));
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index ded7795e4c3a..37b85b721ddf 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2303,7 +2303,7 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st
 	if (!crtc_state->enable_psr2_su_region_et)
 		return;
 
-	intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(crtc->pipe),
+	intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(dev_priv, crtc->pipe),
 		       crtc_state->pipe_srcsz_early_tpt);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index 55e07e87dfbd..4ccbb651016f 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -249,7 +249,7 @@
 /* PSR2 Early transport */
 #define _PIPE_SRCSZ_ERLY_TPT_A	0x70074
 
-#define PIPE_SRCSZ_ERLY_TPT(trans)	_MMIO_TRANS2(dev_priv, trans, _PIPE_SRCSZ_ERLY_TPT_A)
+#define PIPE_SRCSZ_ERLY_TPT(dev_priv, trans)	_MMIO_TRANS2(dev_priv, trans, _PIPE_SRCSZ_ERLY_TPT_A)
 
 #define _SEL_FETCH_PLANE_BASE_1_A		0x70890
 #define _SEL_FETCH_PLANE_BASE_2_A		0x708B0
-- 
2.39.2

[PATCH 16/19] drm/i915: pass dev_priv explicitly to ALPM_CTL

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the ALPM_CTL register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c      | 4 ++--
 drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 37b85b721ddf..fad24b1e5ae2 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1812,7 +1812,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp)
 
 	alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(psr->alpm_parameters.check_entry_lines);
 
-	intel_de_write(dev_priv, ALPM_CTL(cpu_transcoder), alpm_ctl);
+	intel_de_write(dev_priv, ALPM_CTL(dev_priv, cpu_transcoder), alpm_ctl);
 }
 
 static void intel_psr_enable_source(struct intel_dp *intel_dp,
@@ -2112,7 +2112,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 
 	/* Panel Replay on eDP is always using ALPM aux less. */
 	if (intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp)) {
-		intel_de_rmw(dev_priv, ALPM_CTL(cpu_transcoder),
+		intel_de_rmw(dev_priv, ALPM_CTL(dev_priv, cpu_transcoder),
 			     ALPM_CTL_ALPM_ENABLE |
 			     ALPM_CTL_ALPM_AUX_LESS_ENABLE, 0);
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index 4ccbb651016f..4d950b22d4f1 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -297,7 +297,7 @@
 						  _SEL_FETCH_PLANE_BASE_1_A)
 
 #define _ALPM_CTL_A	0x60950
-#define ALPM_CTL(tran)	_MMIO_TRANS2(dev_priv, tran, _ALPM_CTL_A)
+#define ALPM_CTL(dev_priv, tran)	_MMIO_TRANS2(dev_priv, tran, _ALPM_CTL_A)
 #define  ALPM_CTL_ALPM_ENABLE				REG_BIT(31)
 #define  ALPM_CTL_ALPM_AUX_LESS_ENABLE			REG_BIT(30)
 #define  ALPM_CTL_LOBF_ENABLE				REG_BIT(29)
-- 
2.39.2

[PATCH 17/19] drm/i915: pass dev_priv explicitly to ALPM_CTL2

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the ALPM_CTL2 register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index 4d950b22d4f1..05dc1c1d4ac2 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -321,7 +321,7 @@
 #define  ALPM_CTL_AUX_LESS_WAKE_TIME(val)		REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK, val)
 
 #define _ALPM_CTL2_A	0x60954
-#define ALPM_CTL2(tran)	_MMIO_TRANS2(dev_priv, tran, _ALPM_CTL2_A)
+#define ALPM_CTL2(dev_priv, tran)	_MMIO_TRANS2(dev_priv, tran, _ALPM_CTL2_A)
 #define  ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK		REG_GENMASK(28, 24)
 #define  ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY(val)		REG_FIELD_PREP(ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK, val)
 #define  ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION_MASK		REG_GENMASK(19, 16)
-- 
2.39.2

[PATCH 18/19] drm/i915: pass dev_priv explicitly to PORT_ALPM_CTL

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PORT_ALPM_CTL register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c      | 6 ++++--
 drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index fad24b1e5ae2..e88f326b78d6 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1790,7 +1790,8 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp)
 			ALPM_CTL_ALPM_AUX_LESS_ENABLE |
 			ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS;
 
-		intel_de_write(dev_priv, PORT_ALPM_CTL(cpu_transcoder),
+		intel_de_write(dev_priv,
+			       PORT_ALPM_CTL(dev_priv, cpu_transcoder),
 			       PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE |
 			       PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) |
 			       PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) |
@@ -2116,7 +2117,8 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 			     ALPM_CTL_ALPM_ENABLE |
 			     ALPM_CTL_ALPM_AUX_LESS_ENABLE, 0);
 
-		intel_de_rmw(dev_priv, PORT_ALPM_CTL(cpu_transcoder),
+		intel_de_rmw(dev_priv,
+			     PORT_ALPM_CTL(dev_priv, cpu_transcoder),
 			     PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE, 0);
 	}
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index 05dc1c1d4ac2..5e52dddacf91 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -335,7 +335,7 @@
 #define  ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES(val)	REG_FIELD_PREP(ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES_MASK, val)
 
 #define _PORT_ALPM_CTL_A			0x16fa2c
-#define PORT_ALPM_CTL(tran)			_MMIO_TRANS2(dev_priv, tran, _PORT_ALPM_CTL_A)
+#define PORT_ALPM_CTL(dev_priv, tran)			_MMIO_TRANS2(dev_priv, tran, _PORT_ALPM_CTL_A)
 #define  PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE	REG_BIT(31)
 #define  PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK	REG_GENMASK(23, 20)
 #define  PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(val)	REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK, val)
-- 
2.39.2

[PATCH 19/19] drm/i915: pass dev_priv explicitly to PORT_ALPM_LFPS_CTL

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PORT_ALPM_LFPS_CTL register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c      | 3 ++-
 drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index e88f326b78d6..664ffda6a86d 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1798,7 +1798,8 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp)
 			       PORT_ALPM_CTL_SILENCE_PERIOD(
 				       psr->alpm_parameters.silence_period_sym_clocks));
 
-		intel_de_write(dev_priv, PORT_ALPM_LFPS_CTL(cpu_transcoder),
+		intel_de_write(dev_priv,
+			       PORT_ALPM_LFPS_CTL(dev_priv, cpu_transcoder),
 			       PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) |
 			       PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(
 				       psr->alpm_parameters.lfps_half_cycle_num_of_syms) |
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index 5e52dddacf91..08c6d488e89d 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -345,7 +345,7 @@
 #define  PORT_ALPM_CTL_SILENCE_PERIOD(val)	REG_FIELD_PREP(PORT_ALPM_CTL_SILENCE_PERIOD_MASK, val)
 
 #define _PORT_ALPM_LFPS_CTL_A					0x16fa30
-#define PORT_ALPM_LFPS_CTL(tran)				_MMIO_TRANS2(dev_priv, tran, _PORT_ALPM_LFPS_CTL_A)
+#define PORT_ALPM_LFPS_CTL(dev_priv, tran)				_MMIO_TRANS2(dev_priv, tran, _PORT_ALPM_LFPS_CTL_A)
 #define  PORT_ALPM_LFPS_CTL_LFPS_START_POLARITY			REG_BIT(31)
 #define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK		REG_GENMASK(27, 24)
 #define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN		7
-- 
2.39.2

✗ Fi.CI.CHECKPATCH: warning for drm/i915/psr: implicit dev_priv removal

[Patchwork]

== Series Details ==

Series: drm/i915/psr: implicit dev_priv removal
URL   : https://patchwork.freedesktop.org/series/133062/
State : warning

== Summary ==

Error: dim checkpatch failed
4414bea058fd drm/i915: pass dev_priv explicitly to TRANS_EXITLINE
51a28d8826c9 drm/i915: pass dev_priv explicitly to EDP_PSR_CTL
631a7715e20a drm/i915: pass dev_priv explicitly to TRANS_PSR_IMR
-:21: ERROR:CODE_INDENT: code indent should use tabs where possible
#21: FILE: drivers/gpu/drm/i915/display/intel_display_irq.c:1459:
+^I^I^I^I           TRANS_PSR_IMR(dev_priv, trans),$

-:21: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#21: FILE: drivers/gpu/drm/i915/display/intel_display_irq.c:1459:
+			intel_uncore_write(uncore,
+				           TRANS_PSR_IMR(dev_priv, trans),

-:22: ERROR:CODE_INDENT: code indent should use tabs where possible
#22: FILE: drivers/gpu/drm/i915/display/intel_display_irq.c:1460:
+^I^I^I^I           0xffffffff);$

total: 2 errors, 0 warnings, 1 checks, 26 lines checked
37d385c3faca drm/i915: pass dev_priv explicitly to TRANS_PSR_IIR
-:21: ERROR:CODE_INDENT: code indent should use tabs where possible
#21: FILE: drivers/gpu/drm/i915/display/intel_display_irq.c:880:
+^I^I^I^I^I^I        intel_dp->psr.transcoder);$

-:21: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#21: FILE: drivers/gpu/drm/i915/display/intel_display_irq.c:880:
+				iir_reg = TRANS_PSR_IIR(dev_priv,
+						        intel_dp->psr.transcoder);

-:31: ERROR:CODE_INDENT: code indent should use tabs where possible
#31: FILE: drivers/gpu/drm/i915/display/intel_display_irq.c:1463:
+^I^I^I^I           TRANS_PSR_IIR(dev_priv, trans),$

-:31: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#31: FILE: drivers/gpu/drm/i915/display/intel_display_irq.c:1463:
+			intel_uncore_write(uncore,
+				           TRANS_PSR_IIR(dev_priv, trans),

-:32: ERROR:CODE_INDENT: code indent should use tabs where possible
#32: FILE: drivers/gpu/drm/i915/display/intel_display_irq.c:1464:
+^I^I^I^I           0xffffffff);$

total: 3 errors, 0 warnings, 2 checks, 44 lines checked
5f85b1c2a7a3 drm/i915: pass dev_priv explicitly to EDP_PSR_AUX_CTL
2d11442dc42f drm/i915: pass dev_priv explicitly to EDP_PSR_AUX_DATA
-:33: WARNING:LONG_LINE: line length of 129 exceeds 100 columns
#33: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:99:
+#define EDP_PSR_AUX_DATA(dev_priv, tran, i)		_MMIO_TRANS2(dev_priv, tran, _SRD_AUX_DATA_A + (i) * 4) /* 5 registers */

total: 0 errors, 1 warnings, 0 checks, 16 lines checked
7f136f40735b drm/i915: pass dev_priv explicitly to EDP_PSR_STATUS
76febc33beee drm/i915: pass dev_priv explicitly to EDP_PSR_PERF_CNT
-:33: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#33: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:129:
+#define EDP_PSR_PERF_CNT(dev_priv, tran)		_MMIO_TRANS2(dev_priv, tran, _SRD_PERF_CNT_A)

total: 0 errors, 1 warnings, 0 checks, 16 lines checked
0a63d51cf987 drm/i915: pass dev_priv explicitly to EDP_PSR_DEBUG
42741c60ab7f drm/i915: pass dev_priv explicitly to EDP_PSR2_CTL
-:38: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#38: FILE: drivers/gpu/drm/i915/display/intel_psr.c:1703:
+		    intel_de_read(dev_priv, EDP_PSR2_CTL(dev_priv, cpu_transcoder)) & EDP_PSR2_ENABLE);

total: 0 errors, 1 warnings, 0 checks, 59 lines checked
4a8d59d66433 drm/i915: pass dev_priv explicitly to PSR_EVENT
-:35: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#35: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:198:
+#define PSR_EVENT(dev_priv, tran)				_MMIO_TRANS2(dev_priv, tran, _PSR_EVENT_TRANS_A)

total: 0 errors, 1 warnings, 0 checks, 18 lines checked
2ba426ccfe37 drm/i915: pass dev_priv explicitly to EDP_PSR2_STATUS
8ef26fa40b7a drm/i915: pass dev_priv explicitly to _PSR2_SU_STATUS
-:21: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#21: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:224:
+#define _PSR2_SU_STATUS(dev_priv, tran, index)	_MMIO_TRANS2(dev_priv, tran, _PSR2_SU_STATUS_A + (index) * 4)

total: 0 errors, 1 warnings, 0 checks, 10 lines checked
9e6f8599023f drm/i915: pass dev_priv explicitly to PSR2_MAN_TRK_CTL
-:98: WARNING:LONG_LINE: line length of 129 exceeds 100 columns
#98: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:232:
+#define PSR2_MAN_TRK_CTL(dev_priv, tran)					_MMIO_TRANS2(dev_priv, tran, _PSR2_MAN_TRK_CTL_A)

total: 0 errors, 1 warnings, 0 checks, 75 lines checked
f87911fe266b drm/i915: pass dev_priv explicitly to PIPE_SRCSZ_ERLY_TPT
-:46: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#46: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:252:
+#define PIPE_SRCSZ_ERLY_TPT(dev_priv, trans)	_MMIO_TRANS2(dev_priv, trans, _PIPE_SRCSZ_ERLY_TPT_A)

total: 0 errors, 1 warnings, 0 checks, 24 lines checked
e418b54f179f drm/i915: pass dev_priv explicitly to ALPM_CTL
fd717669b583 drm/i915: pass dev_priv explicitly to ALPM_CTL2
86fc46b1dacb drm/i915: pass dev_priv explicitly to PORT_ALPM_CTL
-:44: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#44: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:338:
+#define PORT_ALPM_CTL(dev_priv, tran)			_MMIO_TRANS2(dev_priv, tran, _PORT_ALPM_CTL_A)

total: 0 errors, 1 warnings, 0 checks, 26 lines checked
545ca8b0ad8e drm/i915: pass dev_priv explicitly to PORT_ALPM_LFPS_CTL
-:34: WARNING:LONG_LINE: line length of 123 exceeds 100 columns
#34: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:348:
+#define PORT_ALPM_LFPS_CTL(dev_priv, tran)				_MMIO_TRANS2(dev_priv, tran, _PORT_ALPM_LFPS_CTL_A)

total: 0 errors, 1 warnings, 0 checks, 17 lines checked

✗ Fi.CI.SPARSE: warning for drm/i915/psr: implicit dev_priv removal

[Patchwork]

== Series Details ==

Series: drm/i915/psr: implicit dev_priv removal
URL   : https://patchwork.freedesktop.org/series/133062/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2

✓ Fi.CI.BAT: success for drm/i915/psr: implicit dev_priv removal

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 10487 bytes --]

== Series Details ==

Series: drm/i915/psr: implicit dev_priv removal
URL   : https://patchwork.freedesktop.org/series/133062/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14679 -> Patchwork_133062v1
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/index.html

Participating hosts (37 -> 36)
------------------------------

  Additional (3): bat-dg1-7 bat-atsm-1 fi-bsw-n3050 
  Missing    (4): bat-mtlp-8 bat-dg2-11 bat-jsl-1 fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_133062v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_huc_copy@huc-copy:
    - bat-atsm-1:         NOTRUN -> [FAIL][1] ([i915#10563])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/bat-atsm-1/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@random-engines:
    - fi-bsw-n3050:       NOTRUN -> [SKIP][2] +19 other tests skip
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/fi-bsw-n3050/igt@gem_lmem_swapping@random-engines.html

  * igt@gem_mmap@basic:
    - bat-atsm-1:         NOTRUN -> [SKIP][3] ([i915#4083])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/bat-atsm-1/igt@gem_mmap@basic.html
    - bat-dg1-7:          NOTRUN -> [SKIP][4] ([i915#4083])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/bat-dg1-7/igt@gem_mmap@basic.html

  * igt@gem_tiled_fence_blits@basic:
    - bat-dg1-7:          NOTRUN -> [SKIP][5] ([i915#4077]) +2 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/bat-dg1-7/igt@gem_tiled_fence_blits@basic.html

  * igt@gem_tiled_pread_basic:
    - bat-atsm-1:         NOTRUN -> [SKIP][6] ([i915#4079]) +1 other test skip
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/bat-atsm-1/igt@gem_tiled_pread_basic.html
    - bat-dg1-7:          NOTRUN -> [SKIP][7] ([i915#4079]) +1 other test skip
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/bat-dg1-7/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
    - bat-dg1-7:          NOTRUN -> [SKIP][8] ([i915#6621])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/bat-dg1-7/igt@i915_pm_rps@basic-api.html
    - bat-atsm-1:         NOTRUN -> [SKIP][9] ([i915#6621])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/bat-atsm-1/igt@i915_pm_rps@basic-api.html

  * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
    - bat-dg1-7:          NOTRUN -> [SKIP][10] ([i915#4212]) +7 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/bat-dg1-7/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
    - bat-dg1-7:          NOTRUN -> [SKIP][11] ([i915#4215])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/bat-dg1-7/igt@kms_addfb_basic@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@size-max:
    - bat-atsm-1:         NOTRUN -> [SKIP][12] ([i915#6077]) +37 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/bat-atsm-1/igt@kms_addfb_basic@size-max.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - bat-dg1-7:          NOTRUN -> [SKIP][13] ([i915#4103] / [i915#4213]) +1 other test skip
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/bat-dg1-7/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
    - bat-atsm-1:         NOTRUN -> [SKIP][14] ([i915#6078]) +22 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/bat-atsm-1/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html

  * igt@kms_dsc@dsc-basic:
    - bat-dg1-7:          NOTRUN -> [SKIP][15] ([i915#3555] / [i915#3840])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/bat-dg1-7/igt@kms_dsc@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
    - bat-dg1-7:          NOTRUN -> [SKIP][16]
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/bat-dg1-7/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_force_connector_basic@prune-stale-modes:
    - bat-atsm-1:         NOTRUN -> [SKIP][17] ([i915#6093]) +4 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/bat-atsm-1/igt@kms_force_connector_basic@prune-stale-modes.html

  * igt@kms_hdmi_inject@inject-audio:
    - bat-dg1-7:          NOTRUN -> [SKIP][18] ([i915#433])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/bat-dg1-7/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24:
    - bat-atsm-1:         NOTRUN -> [SKIP][19] ([i915#1836]) +6 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/bat-atsm-1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24.html

  * igt@kms_pm_backlight@basic-brightness:
    - bat-dg1-7:          NOTRUN -> [SKIP][20] ([i915#5354])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/bat-dg1-7/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_prop_blob@basic:
    - bat-atsm-1:         NOTRUN -> [SKIP][21] ([i915#7357])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/bat-atsm-1/igt@kms_prop_blob@basic.html

  * igt@kms_psr@psr-primary-page-flip:
    - bat-dg1-7:          NOTRUN -> [SKIP][22] ([i915#1072] / [i915#9732]) +3 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/bat-dg1-7/igt@kms_psr@psr-primary-page-flip.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-atsm-1:         NOTRUN -> [SKIP][23] ([i915#6094])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/bat-atsm-1/igt@kms_setmode@basic-clone-single-crtc.html
    - bat-dg1-7:          NOTRUN -> [SKIP][24] ([i915#3555])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/bat-dg1-7/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-flip:
    - bat-dg1-7:          NOTRUN -> [SKIP][25] ([i915#3708]) +3 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/bat-dg1-7/igt@prime_vgem@basic-fence-flip.html

  * igt@prime_vgem@basic-fence-mmap:
    - bat-atsm-1:         NOTRUN -> [SKIP][26] ([i915#4077]) +4 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/bat-atsm-1/igt@prime_vgem@basic-fence-mmap.html
    - bat-dg1-7:          NOTRUN -> [SKIP][27] ([i915#3708] / [i915#4077]) +1 other test skip
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/bat-dg1-7/igt@prime_vgem@basic-fence-mmap.html

  * igt@prime_vgem@basic-write:
    - bat-atsm-1:         NOTRUN -> [SKIP][28] +2 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/bat-atsm-1/igt@prime_vgem@basic-write.html

  
#### Possible fixes ####

  * igt@kms_flip@basic-flip-vs-modeset@a-dp6:
    - {bat-mtlp-9}:       [DMESG-WARN][29] ([i915#10435]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/bat-mtlp-9/igt@kms_flip@basic-flip-vs-modeset@a-dp6.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/bat-mtlp-9/igt@kms_flip@basic-flip-vs-modeset@a-dp6.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24@pipe-a-dp-6:
    - {bat-mtlp-9}:       [DMESG-WARN][31] ([i915#10435] / [i915#9157]) -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/bat-mtlp-9/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24@pipe-a-dp-6.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/bat-mtlp-9/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24@pipe-a-dp-6.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#10435]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10435
  [i915#10436]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10436
  [i915#10563]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10563
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#1836]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1836
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
  [i915#4215]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4215
  [i915#433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/433
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#6077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6077
  [i915#6078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6078
  [i915#6093]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6093
  [i915#6094]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6094
  [i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
  [i915#7357]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7357
  [i915#9157]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9157
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732


Build changes
-------------

  * Linux: CI_DRM_14679 -> Patchwork_133062v1

  CI-20190529: 20190529
  CI_DRM_14679: 39bf0b9d268e460fe2b7e9f792c9d610655eb9b7 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7826: ce6ce0f60dd1a6c0df93a01ad71a31964158a2cf @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_133062v1: 39bf0b9d268e460fe2b7e9f792c9d610655eb9b7 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/index.html

[-- Attachment #2: Type: text/html, Size: 12275 bytes --]

✗ Fi.CI.IGT: failure for drm/i915/psr: implicit dev_priv removal

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 69589 bytes --]

== Series Details ==

Series: drm/i915/psr: implicit dev_priv removal
URL   : https://patchwork.freedesktop.org/series/133062/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_14679_full -> Patchwork_133062v1_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_133062v1_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_133062v1_full, please notify your bug team ('I915-ci-infra@lists.freedesktop.org') to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 10)
------------------------------

  Additional (1): shard-snb-0 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_133062v1_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_atomic_transition@plane-all-transition@pipe-b-hdmi-a-4:
    - shard-dg1:          [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-dg1-16/igt@kms_atomic_transition@plane-all-transition@pipe-b-hdmi-a-4.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-15/igt@kms_atomic_transition@plane-all-transition@pipe-b-hdmi-a-4.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank@a-vga1:
    - shard-snb:          [PASS][3] -> [FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-snb6/igt@kms_flip@flip-vs-absolute-wf_vblank@a-vga1.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-snb7/igt@kms_flip@flip-vs-absolute-wf_vblank@a-vga1.html

  
Known issues
------------

  Here are the changes found in Patchwork_133062v1_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@render-ccs:
    - shard-dg2:          NOTRUN -> [FAIL][5] ([i915#10380])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-6/igt@api_intel_bb@render-ccs.html

  * igt@device_reset@cold-reset-bound:
    - shard-rkl:          NOTRUN -> [SKIP][6] ([i915#7701])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-2/igt@device_reset@cold-reset-bound.html

  * igt@drm_fdinfo@virtual-idle:
    - shard-rkl:          NOTRUN -> [FAIL][7] ([i915#7742])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-6/igt@drm_fdinfo@virtual-idle.html

  * igt@gem_ccs@suspend-resume:
    - shard-rkl:          NOTRUN -> [SKIP][8] ([i915#9323])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-2/igt@gem_ccs@suspend-resume.html

  * igt@gem_create@create-ext-cpu-access-big:
    - shard-rkl:          NOTRUN -> [SKIP][9] ([i915#6335])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-3/igt@gem_create@create-ext-cpu-access-big.html

  * igt@gem_create@create-ext-cpu-access-sanity-check:
    - shard-mtlp:         NOTRUN -> [SKIP][10] ([i915#6335])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-mtlp-4/igt@gem_create@create-ext-cpu-access-sanity-check.html

  * igt@gem_ctx_isolation@preservation-s3@vecs1:
    - shard-dg2:          [PASS][11] -> [FAIL][12] ([i915#10086]) +5 other tests fail
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-dg2-3/igt@gem_ctx_isolation@preservation-s3@vecs1.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-11/igt@gem_ctx_isolation@preservation-s3@vecs1.html

  * igt@gem_eio@kms:
    - shard-tglu:         [PASS][13] -> [INCOMPLETE][14] ([i915#10513])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-tglu-2/igt@gem_eio@kms.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-tglu-3/igt@gem_eio@kms.html
    - shard-dg2:          [PASS][15] -> [INCOMPLETE][16] ([i915#10513])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-dg2-11/igt@gem_eio@kms.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-1/igt@gem_eio@kms.html

  * igt@gem_exec_balancer@bonded-semaphore:
    - shard-dg2:          NOTRUN -> [SKIP][17] ([i915#4812])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-6/igt@gem_exec_balancer@bonded-semaphore.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-rkl:          NOTRUN -> [FAIL][18] ([i915#2846])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-6/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-none-share:
    - shard-dg1:          NOTRUN -> [SKIP][19] ([i915#3539] / [i915#4852]) +2 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-13/igt@gem_exec_fair@basic-none-share.html
    - shard-mtlp:         NOTRUN -> [SKIP][20] ([i915#4473] / [i915#4771])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-mtlp-4/igt@gem_exec_fair@basic-none-share.html

  * igt@gem_exec_fair@basic-none-vip@rcs0:
    - shard-glk:          NOTRUN -> [FAIL][21] ([i915#2842]) +1 other test fail
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-glk2/igt@gem_exec_fair@basic-none-vip@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs0:
    - shard-rkl:          NOTRUN -> [FAIL][22] ([i915#2842]) +3 other tests fail
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-2/igt@gem_exec_fair@basic-none@vcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-rkl:          [PASS][23] -> [FAIL][24] ([i915#2842])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-rkl-3/igt@gem_exec_fair@basic-pace-solo@rcs0.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-5/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_exec_fence@concurrent:
    - shard-mtlp:         NOTRUN -> [SKIP][25] ([i915#4812])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-mtlp-4/igt@gem_exec_fence@concurrent.html
    - shard-dg1:          NOTRUN -> [SKIP][26] ([i915#4812])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-13/igt@gem_exec_fence@concurrent.html

  * igt@gem_exec_flush@basic-wb-pro-default:
    - shard-dg2:          NOTRUN -> [SKIP][27] ([i915#3539] / [i915#4852])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-6/igt@gem_exec_flush@basic-wb-pro-default.html

  * igt@gem_exec_reloc@basic-cpu-gtt-noreloc:
    - shard-dg1:          NOTRUN -> [SKIP][28] ([i915#3281]) +1 other test skip
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-15/igt@gem_exec_reloc@basic-cpu-gtt-noreloc.html

  * igt@gem_exec_reloc@basic-gtt-wc-noreloc:
    - shard-rkl:          NOTRUN -> [SKIP][29] ([i915#3281]) +16 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-2/igt@gem_exec_reloc@basic-gtt-wc-noreloc.html

  * igt@gem_exec_reloc@basic-write-gtt-noreloc:
    - shard-dg2:          NOTRUN -> [SKIP][30] ([i915#3281]) +4 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-6/igt@gem_exec_reloc@basic-write-gtt-noreloc.html

  * igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible:
    - shard-dg2:          NOTRUN -> [SKIP][31] ([i915#4860])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-6/igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible.html

  * igt@gem_lmem_swapping@heavy-multi@lmem0:
    - shard-dg2:          [PASS][32] -> [FAIL][33] ([i915#10378])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-dg2-8/igt@gem_lmem_swapping@heavy-multi@lmem0.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-11/igt@gem_lmem_swapping@heavy-multi@lmem0.html

  * igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0:
    - shard-dg2:          [PASS][34] -> [FAIL][35] ([i915#10446])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-dg2-2/igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-4/igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0.html

  * igt@gem_lmem_swapping@heavy-verify-multi@lmem0:
    - shard-dg1:          [PASS][36] -> [FAIL][37] ([i915#10378])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-dg1-13/igt@gem_lmem_swapping@heavy-verify-multi@lmem0.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-16/igt@gem_lmem_swapping@heavy-verify-multi@lmem0.html

  * igt@gem_lmem_swapping@heavy-verify-random-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][38] ([i915#4613]) +2 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-2/igt@gem_lmem_swapping@heavy-verify-random-ccs.html

  * igt@gem_lmem_swapping@smem-oom:
    - shard-glk:          NOTRUN -> [SKIP][39] ([i915#4613]) +4 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-glk5/igt@gem_lmem_swapping@smem-oom.html

  * igt@gem_media_vme:
    - shard-dg1:          NOTRUN -> [SKIP][40] ([i915#284])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-15/igt@gem_media_vme.html

  * igt@gem_mmap_gtt@basic-read-write:
    - shard-mtlp:         NOTRUN -> [SKIP][41] ([i915#4077]) +2 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-mtlp-4/igt@gem_mmap_gtt@basic-read-write.html

  * igt@gem_mmap_gtt@cpuset-basic-small-copy:
    - shard-dg1:          NOTRUN -> [SKIP][42] ([i915#4077]) +5 other tests skip
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-13/igt@gem_mmap_gtt@cpuset-basic-small-copy.html

  * igt@gem_mmap_wc@bad-size:
    - shard-dg2:          NOTRUN -> [SKIP][43] ([i915#4083])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-6/igt@gem_mmap_wc@bad-size.html

  * igt@gem_mmap_wc@copy:
    - shard-dg1:          NOTRUN -> [SKIP][44] ([i915#4083]) +3 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-15/igt@gem_mmap_wc@copy.html

  * igt@gem_mmap_wc@read-write:
    - shard-mtlp:         NOTRUN -> [SKIP][45] ([i915#4083]) +1 other test skip
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-mtlp-4/igt@gem_mmap_wc@read-write.html

  * igt@gem_pread@snoop:
    - shard-dg2:          NOTRUN -> [SKIP][46] ([i915#3282])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-6/igt@gem_pread@snoop.html
    - shard-rkl:          NOTRUN -> [SKIP][47] ([i915#3282]) +1 other test skip
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-3/igt@gem_pread@snoop.html

  * igt@gem_pxp@reject-modify-context-protection-off-2:
    - shard-dg1:          NOTRUN -> [SKIP][48] ([i915#4270])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-15/igt@gem_pxp@reject-modify-context-protection-off-2.html

  * igt@gem_pxp@verify-pxp-execution-after-suspend-resume:
    - shard-rkl:          NOTRUN -> [SKIP][49] ([i915#4270]) +2 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-6/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html

  * igt@gem_render_copy@mixed-tiled-to-yf-tiled-ccs:
    - shard-dg2:          NOTRUN -> [SKIP][50] ([i915#5190] / [i915#8428]) +1 other test skip
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-6/igt@gem_render_copy@mixed-tiled-to-yf-tiled-ccs.html

  * igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled:
    - shard-mtlp:         NOTRUN -> [SKIP][51] ([i915#8428])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-mtlp-4/igt@gem_render_copy@yf-tiled-ccs-to-yf-tiled.html

  * igt@gem_set_tiling_vs_blt@untiled-to-tiled:
    - shard-dg2:          NOTRUN -> [SKIP][52] ([i915#4079])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-6/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html
    - shard-rkl:          NOTRUN -> [SKIP][53] ([i915#8411])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-3/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html

  * igt@gem_userptr_blits@access-control:
    - shard-mtlp:         NOTRUN -> [SKIP][54] ([i915#3297])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-mtlp-4/igt@gem_userptr_blits@access-control.html
    - shard-dg1:          NOTRUN -> [SKIP][55] ([i915#3297])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-13/igt@gem_userptr_blits@access-control.html

  * igt@gem_userptr_blits@dmabuf-unsync:
    - shard-dg2:          NOTRUN -> [SKIP][56] ([i915#3297])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-6/igt@gem_userptr_blits@dmabuf-unsync.html

  * igt@gem_userptr_blits@unsync-unmap-cycles:
    - shard-rkl:          NOTRUN -> [SKIP][57] ([i915#3297]) +2 other tests skip
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-4/igt@gem_userptr_blits@unsync-unmap-cycles.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-dg2:          NOTRUN -> [SKIP][58] ([i915#2856])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-6/igt@gen9_exec_parse@allowed-all.html

  * igt@gen9_exec_parse@bb-chained:
    - shard-rkl:          NOTRUN -> [SKIP][59] ([i915#2527]) +3 other tests skip
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-2/igt@gen9_exec_parse@bb-chained.html

  * igt@gen9_exec_parse@bb-start-cmd:
    - shard-dg1:          NOTRUN -> [SKIP][60] ([i915#2527])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-13/igt@gen9_exec_parse@bb-start-cmd.html
    - shard-mtlp:         NOTRUN -> [SKIP][61] ([i915#2856])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-mtlp-4/igt@gen9_exec_parse@bb-start-cmd.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-rkl:          [PASS][62] -> [ABORT][63] ([i915#9820])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-rkl-5/igt@i915_module_load@reload-with-fault-injection.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-5/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_freq_api@freq-suspend:
    - shard-rkl:          NOTRUN -> [SKIP][64] ([i915#8399]) +1 other test skip
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-2/igt@i915_pm_freq_api@freq-suspend.html

  * igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0:
    - shard-dg1:          [PASS][65] -> [FAIL][66] ([i915#3591])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-18/igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0.html

  * igt@i915_pm_rpm@gem-execbuf-stress-pc8:
    - shard-mtlp:         NOTRUN -> [SKIP][67] +5 other tests skip
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-mtlp-4/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html

  * igt@i915_pm_sseu@full-enable:
    - shard-dg1:          NOTRUN -> [SKIP][68] ([i915#4387])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-13/igt@i915_pm_sseu@full-enable.html
    - shard-mtlp:         NOTRUN -> [SKIP][69] ([i915#8437])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-mtlp-4/igt@i915_pm_sseu@full-enable.html

  * igt@i915_query@test-query-geometry-subslices:
    - shard-rkl:          NOTRUN -> [SKIP][70] ([i915#5723])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-6/igt@i915_query@test-query-geometry-subslices.html

  * igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling:
    - shard-dg1:          NOTRUN -> [SKIP][71] ([i915#4212]) +1 other test skip
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-13/igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling.html

  * igt@kms_addfb_basic@addfb25-x-tiled-legacy:
    - shard-mtlp:         NOTRUN -> [SKIP][72] ([i915#4212])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-mtlp-4/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-2-y-rc-ccs-cc:
    - shard-rkl:          NOTRUN -> [SKIP][73] ([i915#8709]) +3 other tests skip
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-3/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-2-y-rc-ccs-cc.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-3-4-mc-ccs:
    - shard-dg2:          NOTRUN -> [SKIP][74] ([i915#8709]) +11 other tests skip
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-6/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-3-4-mc-ccs.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-mtlp:         NOTRUN -> [SKIP][75] ([i915#1769] / [i915#3555])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-mtlp-4/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html

  * igt@kms_big_fb@4-tiled-16bpp-rotate-0:
    - shard-dg1:          NOTRUN -> [SKIP][76] ([i915#4538] / [i915#5286]) +1 other test skip
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-15/igt@kms_big_fb@4-tiled-16bpp-rotate-0.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-0:
    - shard-rkl:          NOTRUN -> [SKIP][77] ([i915#5286]) +5 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-3/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html

  * igt@kms_big_fb@linear-64bpp-rotate-90:
    - shard-dg1:          NOTRUN -> [SKIP][78] ([i915#3638])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-13/igt@kms_big_fb@linear-64bpp-rotate-90.html

  * igt@kms_big_fb@linear-8bpp-rotate-270:
    - shard-rkl:          NOTRUN -> [SKIP][79] ([i915#3638]) +3 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-2/igt@kms_big_fb@linear-8bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-tglu:         [PASS][80] -> [FAIL][81] ([i915#3743])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-tglu-4/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-tglu-6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-dg2:          NOTRUN -> [SKIP][82] ([i915#4538] / [i915#5190]) +1 other test skip
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-6/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - shard-dg1:          NOTRUN -> [SKIP][83] ([i915#4538]) +1 other test skip
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-13/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_joiner@basic:
    - shard-dg2:          NOTRUN -> [SKIP][84] ([i915#10656])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-6/igt@kms_big_joiner@basic.html
    - shard-rkl:          NOTRUN -> [SKIP][85] ([i915#10656]) +1 other test skip
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-3/igt@kms_big_joiner@basic.html

  * igt@kms_ccs@bad-pixel-format-yf-tiled-ccs@pipe-c-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][86] ([i915#6095]) +11 other tests skip
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-mtlp-4/igt@kms_ccs@bad-pixel-format-yf-tiled-ccs@pipe-c-edp-1.html

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs@pipe-b-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][87] ([i915#10307] / [i915#6095]) +166 other tests skip
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-4/igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][88] ([i915#10307] / [i915#10434] / [i915#6095])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-4/igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][89] ([i915#6095]) +43 other tests skip
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-2/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-a-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [SKIP][90] ([i915#6095]) +67 other tests skip
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-13/igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-a-hdmi-a-3.html

  * igt@kms_cdclk@mode-transition-all-outputs:
    - shard-rkl:          NOTRUN -> [SKIP][91] ([i915#3742])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-4/igt@kms_cdclk@mode-transition-all-outputs.html

  * igt@kms_chamelium_frames@dp-crc-single:
    - shard-dg2:          NOTRUN -> [SKIP][92] ([i915#7828])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-6/igt@kms_chamelium_frames@dp-crc-single.html

  * igt@kms_chamelium_frames@vga-frame-dump:
    - shard-rkl:          NOTRUN -> [SKIP][93] ([i915#7828]) +6 other tests skip
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-6/igt@kms_chamelium_frames@vga-frame-dump.html

  * igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][94] ([i915#7828]) +1 other test skip
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-mtlp-4/igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode.html

  * igt@kms_chamelium_hpd@vga-hpd-for-each-pipe:
    - shard-dg1:          NOTRUN -> [SKIP][95] ([i915#7828]) +3 other tests skip
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-15/igt@kms_chamelium_hpd@vga-hpd-for-each-pipe.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][96] ([i915#7118] / [i915#9424])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-2/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@lic-type-0:
    - shard-dg2:          NOTRUN -> [SKIP][97] ([i915#9424])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-1/igt@kms_content_protection@lic-type-0.html

  * igt@kms_content_protection@uevent@pipe-a-dp-4:
    - shard-dg2:          NOTRUN -> [FAIL][98] ([i915#1339] / [i915#7173])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-11/igt@kms_content_protection@uevent@pipe-a-dp-4.html

  * igt@kms_cursor_crc@cursor-offscreen-32x32:
    - shard-dg1:          NOTRUN -> [SKIP][99] ([i915#3555]) +1 other test skip
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-15/igt@kms_cursor_crc@cursor-offscreen-32x32.html

  * igt@kms_cursor_crc@cursor-offscreen-64x21:
    - shard-mtlp:         NOTRUN -> [SKIP][100] ([i915#8814])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-mtlp-4/igt@kms_cursor_crc@cursor-offscreen-64x21.html

  * igt@kms_cursor_crc@cursor-random-512x170:
    - shard-rkl:          NOTRUN -> [SKIP][101] ([i915#3359]) +1 other test skip
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-4/igt@kms_cursor_crc@cursor-random-512x170.html

  * igt@kms_cursor_crc@cursor-sliding-512x512:
    - shard-dg1:          NOTRUN -> [SKIP][102] ([i915#3359])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-15/igt@kms_cursor_crc@cursor-sliding-512x512.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - shard-mtlp:         NOTRUN -> [SKIP][103] ([i915#4213])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-mtlp-4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
    - shard-dg1:          NOTRUN -> [SKIP][104] ([i915#4103] / [i915#4213])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-13/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
    - shard-mtlp:         NOTRUN -> [SKIP][105] ([i915#9809])
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-mtlp-4/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html

  * igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][106] ([i915#9723])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-2/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-1.html

  * igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][107] ([i915#9723])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-14/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-4.html

  * igt@kms_display_modes@extended-mode-basic:
    - shard-mtlp:         NOTRUN -> [SKIP][108] ([i915#3555] / [i915#8827])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-mtlp-4/igt@kms_display_modes@extended-mode-basic.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][109] ([i915#3804])
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-4/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html

  * igt@kms_dp_aux_dev:
    - shard-dg2:          [PASS][110] -> [SKIP][111] ([i915#1257])
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-dg2-11/igt@kms_dp_aux_dev.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-6/igt@kms_dp_aux_dev.html
    - shard-dg1:          NOTRUN -> [SKIP][112] ([i915#1257])
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-15/igt@kms_dp_aux_dev.html

  * igt@kms_dsc@dsc-with-bpc-formats:
    - shard-dg1:          NOTRUN -> [SKIP][113] ([i915#3555] / [i915#3840])
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-15/igt@kms_dsc@dsc-with-bpc-formats.html

  * igt@kms_dsc@dsc-with-output-formats:
    - shard-rkl:          NOTRUN -> [SKIP][114] ([i915#3555] / [i915#3840])
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-2/igt@kms_dsc@dsc-with-output-formats.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc:
    - shard-dg2:          NOTRUN -> [SKIP][115] ([i915#3840] / [i915#9053])
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-6/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
    - shard-rkl:          NOTRUN -> [SKIP][116] ([i915#3840] / [i915#9053])
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-3/igt@kms_dsc@dsc-with-output-formats-with-bpc.html

  * igt@kms_feature_discovery@chamelium:
    - shard-rkl:          NOTRUN -> [SKIP][117] ([i915#4854])
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-6/igt@kms_feature_discovery@chamelium.html

  * igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset:
    - shard-dg2:          NOTRUN -> [SKIP][118] +5 other tests skip
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-6/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset.html

  * igt@kms_flip@2x-flip-vs-rmfb-interruptible@ab-vga1-hdmi-a1:
    - shard-snb:          [PASS][119] -> [ABORT][120] ([i915#8852])
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-snb5/igt@kms_flip@2x-flip-vs-rmfb-interruptible@ab-vga1-hdmi-a1.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-snb5/igt@kms_flip@2x-flip-vs-rmfb-interruptible@ab-vga1-hdmi-a1.html

  * igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
    - shard-mtlp:         NOTRUN -> [SKIP][121] ([i915#3637]) +1 other test skip
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-mtlp-4/igt@kms_flip@2x-modeset-vs-vblank-race-interruptible.html

  * igt@kms_flip@2x-wf_vblank-ts-check-interruptible:
    - shard-dg1:          NOTRUN -> [SKIP][122] ([i915#9934]) +4 other tests skip
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-15/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank@a-hdmi-a1:
    - shard-snb:          [PASS][123] -> [FAIL][124] ([i915#2122]) +3 other tests fail
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-snb6/igt@kms_flip@flip-vs-absolute-wf_vblank@a-hdmi-a1.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-snb7/igt@kms_flip@flip-vs-absolute-wf_vblank@a-hdmi-a1.html

  * igt@kms_flip@flip-vs-fences-interruptible:
    - shard-dg1:          NOTRUN -> [SKIP][125] ([i915#8381])
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-13/igt@kms_flip@flip-vs-fences-interruptible.html
    - shard-mtlp:         NOTRUN -> [SKIP][126] ([i915#8381])
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-mtlp-4/igt@kms_flip@flip-vs-fences-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
    - shard-dg2:          NOTRUN -> [SKIP][127] ([i915#2672])
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-6/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html
    - shard-rkl:          NOTRUN -> [SKIP][128] ([i915#2672]) +3 other tests skip
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-3/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][129] ([i915#2672])
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-mtlp-4/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][130] ([i915#2672] / [i915#3555])
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-mtlp-4/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html

  * igt@kms_force_connector_basic@prune-stale-modes:
    - shard-mtlp:         NOTRUN -> [SKIP][131] ([i915#5274])
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-mtlp-4/igt@kms_force_connector_basic@prune-stale-modes.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render:
    - shard-snb:          [PASS][132] -> [SKIP][133]
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-snb2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-snb4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-wc:
    - shard-dg2:          NOTRUN -> [SKIP][134] ([i915#8708]) +3 other tests skip
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-4:
    - shard-rkl:          NOTRUN -> [SKIP][135] ([i915#5439])
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-3/igt@kms_frontbuffer_tracking@fbc-tiling-4.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack-mmap-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][136] ([i915#8708]) +1 other test skip
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-mtlp-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite:
    - shard-dg1:          NOTRUN -> [SKIP][137] ([i915#3458]) +8 other tests skip
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-13/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt:
    - shard-rkl:          NOTRUN -> [SKIP][138] ([i915#1825]) +34 other tests skip
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-mtlp:         NOTRUN -> [SKIP][139] ([i915#1825]) +8 other tests skip
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-mtlp-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-stridechange:
    - shard-dg2:          NOTRUN -> [SKIP][140] ([i915#3458]) +3 other tests skip
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-6/igt@kms_frontbuffer_tracking@fbcpsr-stridechange.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite:
    - shard-rkl:          NOTRUN -> [SKIP][141] ([i915#3023]) +21 other tests skip
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-onoff:
    - shard-dg1:          NOTRUN -> [SKIP][142] +20 other tests skip
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-13/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-dg1:          NOTRUN -> [SKIP][143] ([i915#8708]) +8 other tests skip
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-13/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-plflip-blt:
    - shard-dg2:          NOTRUN -> [SKIP][144] ([i915#5354]) +8 other tests skip
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-plflip-blt.html

  * igt@kms_hdr@bpc-switch:
    - shard-dg2:          NOTRUN -> [SKIP][145] ([i915#3555] / [i915#8228])
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-1/igt@kms_hdr@bpc-switch.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][146] ([i915#3555] / [i915#8228]) +1 other test skip
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-2/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_panel_fitting@atomic-fastset:
    - shard-dg1:          NOTRUN -> [SKIP][147] ([i915#6301])
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-13/igt@kms_panel_fitting@atomic-fastset.html

  * igt@kms_plane@pixel-format-source-clamping@pipe-b:
    - shard-mtlp:         [PASS][148] -> [ABORT][149] ([i915#10698] / [i915#10892])
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-mtlp-6/igt@kms_plane@pixel-format-source-clamping@pipe-b.html
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-mtlp-1/igt@kms_plane@pixel-format-source-clamping@pipe-b.html

  * igt@kms_plane@pixel-format@pipe-b:
    - shard-mtlp:         [PASS][150] -> [ABORT][151] ([i915#10698])
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-mtlp-1/igt@kms_plane@pixel-format@pipe-b.html
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-mtlp-3/igt@kms_plane@pixel-format@pipe-b.html

  * igt@kms_plane_alpha_blend@constant-alpha-max@pipe-c-hdmi-a-1:
    - shard-glk:          NOTRUN -> [FAIL][152] ([i915#10647]) +1 other test fail
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-glk2/igt@kms_plane_alpha_blend@constant-alpha-max@pipe-c-hdmi-a-1.html

  * igt@kms_plane_lowres@tiling-yf:
    - shard-rkl:          NOTRUN -> [SKIP][153] ([i915#3555]) +7 other tests skip
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-6/igt@kms_plane_lowres@tiling-yf.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][154] ([i915#9423]) +5 other tests skip
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-3/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-a-hdmi-a-2.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-b-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][155] ([i915#9423]) +11 other tests skip
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-6/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-b-hdmi-a-3.html

  * igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-d-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [SKIP][156] ([i915#9423]) +3 other tests skip
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-13/igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-d-hdmi-a-3.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][157] ([i915#5235]) +3 other tests skip
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-6/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-hdmi-a-2.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b-dp-4:
    - shard-dg2:          NOTRUN -> [SKIP][158] ([i915#5235] / [i915#9423]) +15 other tests skip
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-11/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b-dp-4.html

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [SKIP][159] ([i915#5235]) +11 other tests skip
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-13/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b-hdmi-a-3.html

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-d-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][160] ([i915#5235]) +3 other tests skip
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-mtlp-4/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-d-edp-1.html

  * igt@kms_pm_backlight@fade-with-suspend:
    - shard-rkl:          NOTRUN -> [SKIP][161] ([i915#5354])
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-6/igt@kms_pm_backlight@fade-with-suspend.html

  * igt@kms_pm_dc@dc3co-vpb-simulation:
    - shard-dg1:          NOTRUN -> [SKIP][162] ([i915#9685])
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-15/igt@kms_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][163] ([i915#3361])
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-4/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-dg2:          NOTRUN -> [SKIP][164] ([i915#9340])
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-6/igt@kms_pm_lpsp@kms-lpsp.html
    - shard-rkl:          NOTRUN -> [SKIP][165] ([i915#9340])
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-3/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@kms_pm_lpsp@screens-disabled:
    - shard-dg1:          NOTRUN -> [SKIP][166] ([i915#8430])
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-13/igt@kms_pm_lpsp@screens-disabled.html
    - shard-mtlp:         NOTRUN -> [SKIP][167] ([i915#8430])
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-mtlp-4/igt@kms_pm_lpsp@screens-disabled.html

  * igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-rkl:          [PASS][168] -> [SKIP][169] ([i915#9519])
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-rkl-6/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-4/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@kms_pm_rpm@fences-dpms:
    - shard-dg2:          NOTRUN -> [SKIP][170] ([i915#4077]) +3 other tests skip
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-6/igt@kms_pm_rpm@fences-dpms.html

  * igt@kms_pm_rpm@modeset-non-lpsp:
    - shard-rkl:          NOTRUN -> [SKIP][171] ([i915#9519])
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-4/igt@kms_pm_rpm@modeset-non-lpsp.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress:
    - shard-dg2:          [PASS][172] -> [SKIP][173] ([i915#9519]) +2 other tests skip
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-dg2-5/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-4/igt@kms_pm_rpm@modeset-non-lpsp-stress.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
    - shard-mtlp:         NOTRUN -> [SKIP][174] ([i915#9519])
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-mtlp-4/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html

  * igt@kms_psr2_sf@fbc-primary-plane-update-sf-dmg-area:
    - shard-rkl:          NOTRUN -> [SKIP][175] +43 other tests skip
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-6/igt@kms_psr2_sf@fbc-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-dg2:          NOTRUN -> [SKIP][176] ([i915#9683])
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-6/igt@kms_psr2_su@page_flip-nv12.html
    - shard-rkl:          NOTRUN -> [SKIP][177] ([i915#9683])
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-3/igt@kms_psr2_su@page_flip-nv12.html

  * igt@kms_psr@fbc-psr2-cursor-mmap-gtt:
    - shard-glk:          NOTRUN -> [SKIP][178] +259 other tests skip
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-glk2/igt@kms_psr@fbc-psr2-cursor-mmap-gtt.html

  * igt@kms_psr@pr-sprite-render:
    - shard-mtlp:         NOTRUN -> [SKIP][179] ([i915#9688]) +3 other tests skip
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-mtlp-4/igt@kms_psr@pr-sprite-render.html

  * igt@kms_psr@psr-primary-mmap-cpu:
    - shard-dg2:          NOTRUN -> [SKIP][180] ([i915#1072] / [i915#9732]) +4 other tests skip
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-6/igt@kms_psr@psr-primary-mmap-cpu.html

  * igt@kms_psr@psr2-cursor-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][181] ([i915#1072] / [i915#9732]) +19 other tests skip
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-3/igt@kms_psr@psr2-cursor-mmap-gtt.html

  * igt@kms_psr@psr2-sprite-mmap-gtt:
    - shard-dg1:          NOTRUN -> [SKIP][182] ([i915#1072] / [i915#9732]) +9 other tests skip
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-15/igt@kms_psr@psr2-sprite-mmap-gtt.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
    - shard-dg2:          NOTRUN -> [SKIP][183] ([i915#5190])
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-6/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
    - shard-dg1:          NOTRUN -> [SKIP][184] ([i915#5289]) +1 other test skip
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-15/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html

  * igt@kms_setmode@invalid-clone-single-crtc:
    - shard-dg2:          NOTRUN -> [SKIP][185] ([i915#3555]) +2 other tests skip
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-6/igt@kms_setmode@invalid-clone-single-crtc.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-dg1:          NOTRUN -> [SKIP][186] ([i915#8623])
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-13/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
    - shard-mtlp:         NOTRUN -> [SKIP][187] ([i915#8623])
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-mtlp-4/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_vblank@ts-continuation-dpms-rpm@pipe-b-vga-1:
    - shard-snb:          NOTRUN -> [SKIP][188] +1 other test skip
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-snb7/igt@kms_vblank@ts-continuation-dpms-rpm@pipe-b-vga-1.html

  * igt@kms_vrr@max-min:
    - shard-rkl:          NOTRUN -> [SKIP][189] ([i915#9906])
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-2/igt@kms_vrr@max-min.html

  * igt@kms_writeback@writeback-check-output:
    - shard-dg1:          NOTRUN -> [SKIP][190] ([i915#2437])
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-15/igt@kms_writeback@writeback-check-output.html

  * igt@kms_writeback@writeback-check-output-xrgb2101010:
    - shard-rkl:          NOTRUN -> [SKIP][191] ([i915#2437] / [i915#9412]) +1 other test skip
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-6/igt@kms_writeback@writeback-check-output-xrgb2101010.html

  * igt@kms_writeback@writeback-fb-id-xrgb2101010:
    - shard-glk:          NOTRUN -> [SKIP][192] ([i915#2437]) +1 other test skip
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-glk8/igt@kms_writeback@writeback-fb-id-xrgb2101010.html

  * igt@perf_pmu@module-unload:
    - shard-dg2:          NOTRUN -> [FAIL][193] ([i915#10537] / [i915#5793])
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-6/igt@perf_pmu@module-unload.html

  * igt@prime_vgem@fence-write-hang:
    - shard-rkl:          NOTRUN -> [SKIP][194] ([i915#3708])
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-4/igt@prime_vgem@fence-write-hang.html

  * igt@runner@aborted:
    - shard-glk:          NOTRUN -> [FAIL][195] ([i915#10291])
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-glk5/igt@runner@aborted.html

  * igt@sriov_basic@bind-unbind-vf:
    - shard-dg2:          NOTRUN -> [SKIP][196] ([i915#9917])
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-6/igt@sriov_basic@bind-unbind-vf.html
    - shard-rkl:          NOTRUN -> [SKIP][197] ([i915#9917])
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-3/igt@sriov_basic@bind-unbind-vf.html

  * igt@syncobj_timeline@invalid-wait-zero-handles:
    - shard-dg1:          NOTRUN -> [FAIL][198] ([i915#9781])
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-13/igt@syncobj_timeline@invalid-wait-zero-handles.html
    - shard-mtlp:         NOTRUN -> [FAIL][199] ([i915#9781])
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-mtlp-4/igt@syncobj_timeline@invalid-wait-zero-handles.html

  * igt@v3d/v3d_job_submission@array-job-submission:
    - shard-dg1:          NOTRUN -> [SKIP][200] ([i915#2575]) +5 other tests skip
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-13/igt@v3d/v3d_job_submission@array-job-submission.html
    - shard-mtlp:         NOTRUN -> [SKIP][201] ([i915#2575]) +2 other tests skip
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-mtlp-4/igt@v3d/v3d_job_submission@array-job-submission.html

  * igt@v3d/v3d_perfmon@create-two-perfmon:
    - shard-dg2:          NOTRUN -> [SKIP][202] ([i915#2575]) +3 other tests skip
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-11/igt@v3d/v3d_perfmon@create-two-perfmon.html

  * igt@vc4/vc4_create_bo@create-bo-zeroed:
    - shard-rkl:          NOTRUN -> [SKIP][203] ([i915#7711]) +8 other tests skip
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-4/igt@vc4/vc4_create_bo@create-bo-zeroed.html

  * igt@vc4/vc4_label_bo@set-bad-name:
    - shard-dg1:          NOTRUN -> [SKIP][204] ([i915#7711]) +1 other test skip
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-13/igt@vc4/vc4_label_bo@set-bad-name.html
    - shard-mtlp:         NOTRUN -> [SKIP][205] ([i915#7711])
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-mtlp-4/igt@vc4/vc4_label_bo@set-bad-name.html

  * igt@vc4/vc4_wait_seqno@bad-seqno-0ns:
    - shard-dg2:          NOTRUN -> [SKIP][206] ([i915#7711]) +1 other test skip
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-6/igt@vc4/vc4_wait_seqno@bad-seqno-0ns.html

  
#### Possible fixes ####

  * igt@gem_ctx_exec@basic-nohangcheck:
    - shard-tglu:         [FAIL][207] ([i915#6268]) -> [PASS][208]
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-tglu-5/igt@gem_ctx_exec@basic-nohangcheck.html
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-tglu-8/igt@gem_ctx_exec@basic-nohangcheck.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-rkl:          [FAIL][209] ([i915#2842]) -> [PASS][210]
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-rkl-1/igt@gem_exec_fair@basic-none-solo@rcs0.html
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-2/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-glk:          [FAIL][211] ([i915#2842]) -> [PASS][212]
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-glk6/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-glk8/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace@rcs0:
    - shard-tglu:         [FAIL][213] ([i915#2876]) -> [PASS][214]
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-tglu-6/igt@gem_exec_fair@basic-pace@rcs0.html
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-tglu-5/igt@gem_exec_fair@basic-pace@rcs0.html

  * igt@gem_lmem_swapping@heavy-verify-random@lmem0:
    - shard-dg2:          [FAIL][215] ([i915#10378]) -> [PASS][216] +1 other test pass
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-dg2-10/igt@gem_lmem_swapping@heavy-verify-random@lmem0.html
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-6/igt@gem_lmem_swapping@heavy-verify-random@lmem0.html

  * igt@gem_lmem_swapping@parallel-random-verify@lmem0:
    - shard-dg2:          [INCOMPLETE][217] ([i915#10317] / [i915#1982]) -> [PASS][218]
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-dg2-3/igt@gem_lmem_swapping@parallel-random-verify@lmem0.html
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-11/igt@gem_lmem_swapping@parallel-random-verify@lmem0.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-mtlp:         [ABORT][219] ([i915#10131] / [i915#10887] / [i915#9820]) -> [PASS][220]
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-mtlp-3/igt@i915_module_load@reload-with-fault-injection.html
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-mtlp-4/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0:
    - shard-dg1:          [FAIL][221] ([i915#3591]) -> [PASS][222] +1 other test pass
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-18/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180:
    - shard-mtlp:         [DMESG-FAIL][223] ([i915#2017]) -> [PASS][224]
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-mtlp-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180.html
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-mtlp-4/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180.html

  * igt@kms_flip@flip-vs-suspend-interruptible@b-hdmi-a1:
    - shard-snb:          [INCOMPLETE][225] ([i915#4839]) -> [PASS][226]
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-snb6/igt@kms_flip@flip-vs-suspend-interruptible@b-hdmi-a1.html
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-snb7/igt@kms_flip@flip-vs-suspend-interruptible@b-hdmi-a1.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt:
    - shard-snb:          [SKIP][227] -> [PASS][228] +6 other tests pass
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-snb6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt.html
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-snb7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt.html

  * igt@kms_pm_rpm@modeset-lpsp-stress-no-wait:
    - shard-rkl:          [SKIP][229] ([i915#9519]) -> [PASS][230]
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-rkl-3/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-rkl-5/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html

  * igt@kms_pm_rpm@modeset-non-lpsp:
    - shard-dg2:          [SKIP][231] ([i915#9519]) -> [PASS][232]
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-dg2-8/igt@kms_pm_rpm@modeset-non-lpsp.html
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-7/igt@kms_pm_rpm@modeset-non-lpsp.html

  * igt@kms_sysfs_edid_timing:
    - shard-dg2:          [FAIL][233] ([IGT#2]) -> [PASS][234]
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-dg2-8/igt@kms_sysfs_edid_timing.html
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-11/igt@kms_sysfs_edid_timing.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1:
    - shard-tglu:         [FAIL][235] ([i915#9196]) -> [PASS][236]
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-tglu-3/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-tglu-7/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html

  * igt@perf_pmu@busy-double-start@vecs1:
    - shard-dg2:          [FAIL][237] ([i915#4349]) -> [PASS][238] +3 other tests pass
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-dg2-3/igt@perf_pmu@busy-double-start@vecs1.html
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-11/igt@perf_pmu@busy-double-start@vecs1.html

  
#### Warnings ####

  * igt@gem_eio@kms:
    - shard-dg1:          [INCOMPLETE][239] ([i915#10513] / [i915#1982]) -> [INCOMPLETE][240] ([i915#10513])
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-dg1-18/igt@gem_eio@kms.html
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg1-15/igt@gem_eio@kms.html

  * igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0:
    - shard-tglu:         [FAIL][241] ([i915#3591]) -> [WARN][242] ([i915#2681])
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-tglu-9/igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0.html
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-tglu-4/igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0.html

  * igt@kms_content_protection@srm:
    - shard-snb:          [SKIP][243] -> [INCOMPLETE][244] ([i915#8816])
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-snb6/igt@kms_content_protection@srm.html
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-snb7/igt@kms_content_protection@srm.html

  * igt@kms_content_protection@type1:
    - shard-dg2:          [SKIP][245] ([i915#7118] / [i915#9424]) -> [SKIP][246] ([i915#7118] / [i915#7162] / [i915#9424])
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-dg2-8/igt@kms_content_protection@type1.html
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-11/igt@kms_content_protection@type1.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-cpu:
    - shard-dg2:          [SKIP][247] ([i915#3458]) -> [SKIP][248] ([i915#10433] / [i915#3458]) +3 other tests skip
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-dg2-5/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-cpu.html
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-cpu.html

  * igt@kms_psr@fbc-psr-cursor-plane-move:
    - shard-dg2:          [SKIP][249] ([i915#1072] / [i915#9732]) -> [SKIP][250] ([i915#1072] / [i915#9673] / [i915#9732]) +20 other tests skip
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-dg2-5/igt@kms_psr@fbc-psr-cursor-plane-move.html
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-11/igt@kms_psr@fbc-psr-cursor-plane-move.html

  * igt@kms_psr@fbc-psr2-sprite-mmap-cpu:
    - shard-dg2:          [SKIP][251] ([i915#1072] / [i915#9673] / [i915#9732]) -> [SKIP][252] ([i915#1072] / [i915#9732]) +7 other tests skip
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-dg2-11/igt@kms_psr@fbc-psr2-sprite-mmap-cpu.html
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-dg2-1/igt@kms_psr@fbc-psr2-sprite-mmap-cpu.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-glk:          [SKIP][253] -> [FAIL][254] ([i915#10959])
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-glk8/igt@kms_tiled_display@basic-test-pattern.html
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/shard-glk7/igt@kms_tiled_display@basic-test-pattern.html

  
  [IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
  [i915#10086]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10086
  [i915#10131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10131
  [i915#10291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10291
  [i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
  [i915#10317]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10317
  [i915#10378]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10378
  [i915#10380]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10380
  [i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
  [i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
  [i915#10446]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10446
  [i915#10513]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10513
  [i915#10537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10537
  [i915#10647]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10647
  [i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
  [i915#10698]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10698
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#10887]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10887
  [i915#10892]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10892
  [i915#10959]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10959
  [i915#1257]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1257
  [i915#1339]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1339
  [i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
  [i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
  [i915#2017]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2017
  [i915#2122]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2122
  [i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
  [i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
  [i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575
  [i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
  [i915#2681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2681
  [i915#284]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/284
  [i915#2842]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2842
  [i915#2846]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2846
  [i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
  [i915#2876]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2876
  [i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
  [i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
  [i915#3359]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3359
  [i915#3361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3361
  [i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
  [i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3591]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3591
  [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
  [i915#3743]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3743
  [i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
  [i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
  [i915#4349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4349
  [i915#4387]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4387
  [i915#4473]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4473
  [i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#4771]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4771
  [i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
  [i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
  [i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
  [i915#4854]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4854
  [i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
  [i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
  [i915#5235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5235
  [i915#5274]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5274
  [i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
  [i915#5723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5723
  [i915#5793]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5793
  [i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
  [i915#6268]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6268
  [i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
  [i915#6335]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6335
  [i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
  [i915#7162]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7162
  [i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173
  [i915#7701]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7701
  [i915#7711]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7711
  [i915#7742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7742
  [i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
  [i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
  [i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
  [i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
  [i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
  [i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
  [i915#8430]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8430
  [i915#8437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8437
  [i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
  [i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
  [i915#8709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8709
  [i915#8814]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8814
  [i915#8816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8816
  [i915#8827]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8827
  [i915#8852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8852
  [i915#9053]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9053
  [i915#9196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9196
  [i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
  [i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340
  [i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
  [i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
  [i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
  [i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519
  [i915#9673]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9673
  [i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
  [i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
  [i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
  [i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9781]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9781
  [i915#9809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9809
  [i915#9820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9820
  [i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
  [i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
  [i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934


Build changes
-------------

  * Linux: CI_DRM_14679 -> Patchwork_133062v1

  CI-20190529: 20190529
  CI_DRM_14679: 39bf0b9d268e460fe2b7e9f792c9d610655eb9b7 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7826: ce6ce0f60dd1a6c0df93a01ad71a31964158a2cf @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_133062v1: 39bf0b9d268e460fe2b7e9f792c9d610655eb9b7 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v1/index.html

[-- Attachment #2: Type: text/html, Size: 83932 bytes --]

Re: [PATCH 01/19] drm/i915: pass dev_priv explicitly to TRANS_EXITLINE

[Rodrigo Vivi]

On Tue, Apr 30, 2024 at 01:09:55PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the TRANS_EXITLINE register macro.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_psr.c      | 7 +++++--
>  drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
>  2 files changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index f5b33335a9ae..1cbd8c6714b1 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1685,7 +1685,8 @@ void intel_psr_get_config(struct intel_encoder *encoder,
>  	}
>  
>  	if (DISPLAY_VER(dev_priv) >= 12) {
> -		val = intel_de_read(dev_priv, TRANS_EXITLINE(cpu_transcoder));
> +		val = intel_de_read(dev_priv,
> +				    TRANS_EXITLINE(dev_priv, cpu_transcoder));
>  		pipe_config->dc3co_exitline = REG_FIELD_GET(EXITLINE_MASK, val);
>  	}
>  unlock:
> @@ -1877,7 +1878,9 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
>  	 * transcoder, EXITLINE will need to be unset when disabling PSR
>  	 */
>  	if (intel_dp->psr.dc3co_exitline)
> -		intel_de_rmw(dev_priv, TRANS_EXITLINE(cpu_transcoder), EXITLINE_MASK,
> +		intel_de_rmw(dev_priv,
> +			     TRANS_EXITLINE(dev_priv, cpu_transcoder),
> +			     EXITLINE_MASK,
>  			     intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT | EXITLINE_ENABLE);
>  
>  	if (HAS_PSR_HW_TRACKING(dev_priv) && HAS_PSR2_SEL_FETCH(dev_priv))
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index ebc22999572c..0e0c71ea9fe3 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -9,7 +9,7 @@
>  #include "intel_display_reg_defs.h"
>  #include "intel_dp_aux_regs.h"
>  
> -#define TRANS_EXITLINE(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_EXITLINE_A)
> +#define TRANS_EXITLINE(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_EXITLINE_A)
>  #define   EXITLINE_ENABLE	REG_BIT(31)
>  #define   EXITLINE_MASK		REG_GENMASK(12, 0)
>  #define   EXITLINE_SHIFT	0
> -- 
> 2.39.2
> 

Re: [PATCH 02/19] drm/i915: pass dev_priv explicitly to EDP_PSR_CTL

[Rodrigo Vivi]

On Tue, Apr 30, 2024 at 01:09:56PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the EDP_PSR_CTL register macro.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_psr.c      | 2 +-
>  drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 1cbd8c6714b1..57414a1375b1 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -269,7 +269,7 @@ static i915_reg_t psr_ctl_reg(struct drm_i915_private *dev_priv,
>  			      enum transcoder cpu_transcoder)
>  {
>  	if (DISPLAY_VER(dev_priv) >= 8)
> -		return EDP_PSR_CTL(cpu_transcoder);
> +		return EDP_PSR_CTL(dev_priv, cpu_transcoder);
>  	else
>  		return HSW_SRD_CTL;
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index 0e0c71ea9fe3..d815f08aac2c 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -23,7 +23,7 @@
>  #define HSW_SRD_CTL				_MMIO(0x64800)
>  #define _SRD_CTL_A				0x60800
>  #define _SRD_CTL_EDP				0x6f800
> -#define EDP_PSR_CTL(tran)			_MMIO_TRANS2(dev_priv, tran, _SRD_CTL_A)
> +#define EDP_PSR_CTL(dev_priv, tran)			_MMIO_TRANS2(dev_priv, tran, _SRD_CTL_A)
>  #define   EDP_PSR_ENABLE			REG_BIT(31)
>  #define   BDW_PSR_SINGLE_FRAME			REG_BIT(30)
>  #define   EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK	REG_BIT(29) /* SW can't modify */
> -- 
> 2.39.2
> 

Re: [PATCH 03/19] drm/i915: pass dev_priv explicitly to TRANS_PSR_IMR

[Rodrigo Vivi]

On Tue, Apr 30, 2024 at 01:09:57PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the TRANS_PSR_IMR register macro.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display_irq.c | 4 +++-
>  drivers/gpu/drm/i915/display/intel_psr.c         | 2 +-
>  drivers/gpu/drm/i915/display/intel_psr_regs.h    | 2 +-
>  3 files changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index c337e0597541..a9bcf249e925 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -1455,7 +1455,9 @@ void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
>  			if (!intel_display_power_is_enabled(dev_priv, domain))
>  				continue;
>  
> -			intel_uncore_write(uncore, TRANS_PSR_IMR(trans), 0xffffffff);
> +			intel_uncore_write(uncore,
> +				           TRANS_PSR_IMR(dev_priv, trans),
> +				           0xffffffff);
>  			intel_uncore_write(uncore, TRANS_PSR_IIR(trans), 0xffffffff);
>  		}
>  	} else {
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 57414a1375b1..12b541e8bbf9 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -305,7 +305,7 @@ static i915_reg_t psr_imr_reg(struct drm_i915_private *dev_priv,
>  			      enum transcoder cpu_transcoder)
>  {
>  	if (DISPLAY_VER(dev_priv) >= 12)
> -		return TRANS_PSR_IMR(cpu_transcoder);
> +		return TRANS_PSR_IMR(dev_priv, cpu_transcoder);
>  	else
>  		return EDP_PSR_IMR;
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index d815f08aac2c..40dc6ee7ec1d 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -66,7 +66,7 @@
>  #define EDP_PSR_IIR				_MMIO(0x64838)
>  #define _PSR_IMR_A				0x60814
>  #define _PSR_IIR_A				0x60818
> -#define TRANS_PSR_IMR(tran)			_MMIO_TRANS2(dev_priv, tran, _PSR_IMR_A)
> +#define TRANS_PSR_IMR(dev_priv, tran)			_MMIO_TRANS2(dev_priv, tran, _PSR_IMR_A)
>  #define TRANS_PSR_IIR(tran)			_MMIO_TRANS2(dev_priv, tran, _PSR_IIR_A)
>  #define   _EDP_PSR_TRANS_SHIFT(trans)		((trans) == TRANSCODER_EDP ? \
>  						 0 : ((trans) - TRANSCODER_A + 1) * 8)
> -- 
> 2.39.2
> 

Re: [PATCH 04/19] drm/i915: pass dev_priv explicitly to TRANS_PSR_IIR

[Rodrigo Vivi]

On Tue, Apr 30, 2024 at 01:09:58PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the TRANS_PSR_IIR register macro.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display_irq.c | 10 +++++++---
>  drivers/gpu/drm/i915/display/intel_psr.c         |  2 +-
>  drivers/gpu/drm/i915/display/intel_psr_regs.h    |  2 +-
>  3 files changed, 9 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index a9bcf249e925..c41f058acaff 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -876,7 +876,8 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
>  			struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  
>  			if (DISPLAY_VER(dev_priv) >= 12)
> -				iir_reg = TRANS_PSR_IIR(intel_dp->psr.transcoder);
> +				iir_reg = TRANS_PSR_IIR(dev_priv,
> +						        intel_dp->psr.transcoder);
>  			else
>  				iir_reg = EDP_PSR_IIR;
>  
> @@ -1458,7 +1459,9 @@ void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
>  			intel_uncore_write(uncore,
>  				           TRANS_PSR_IMR(dev_priv, trans),
>  				           0xffffffff);
> -			intel_uncore_write(uncore, TRANS_PSR_IIR(trans), 0xffffffff);
> +			intel_uncore_write(uncore,
> +				           TRANS_PSR_IIR(dev_priv, trans),
> +				           0xffffffff);
>  		}
>  	} else {
>  		intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
> @@ -1690,7 +1693,8 @@ void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>  			if (!intel_display_power_is_enabled(dev_priv, domain))
>  				continue;
>  
> -			gen3_assert_iir_is_zero(uncore, TRANS_PSR_IIR(trans));
> +			gen3_assert_iir_is_zero(uncore,
> +						TRANS_PSR_IIR(dev_priv, trans));
>  		}
>  	} else {
>  		gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 12b541e8bbf9..0b1f7e62470e 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -314,7 +314,7 @@ static i915_reg_t psr_iir_reg(struct drm_i915_private *dev_priv,
>  			      enum transcoder cpu_transcoder)
>  {
>  	if (DISPLAY_VER(dev_priv) >= 12)
> -		return TRANS_PSR_IIR(cpu_transcoder);
> +		return TRANS_PSR_IIR(dev_priv, cpu_transcoder);
>  	else
>  		return EDP_PSR_IIR;
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index 40dc6ee7ec1d..5fd4f875ade0 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -67,7 +67,7 @@
>  #define _PSR_IMR_A				0x60814
>  #define _PSR_IIR_A				0x60818
>  #define TRANS_PSR_IMR(dev_priv, tran)			_MMIO_TRANS2(dev_priv, tran, _PSR_IMR_A)
> -#define TRANS_PSR_IIR(tran)			_MMIO_TRANS2(dev_priv, tran, _PSR_IIR_A)
> +#define TRANS_PSR_IIR(dev_priv, tran)			_MMIO_TRANS2(dev_priv, tran, _PSR_IIR_A)
>  #define   _EDP_PSR_TRANS_SHIFT(trans)		((trans) == TRANSCODER_EDP ? \
>  						 0 : ((trans) - TRANSCODER_A + 1) * 8)
>  #define   TGL_PSR_MASK			REG_GENMASK(2, 0)
> -- 
> 2.39.2
> 

Re: [PATCH 05/19] drm/i915: pass dev_priv explicitly to EDP_PSR_AUX_CTL

[Rodrigo Vivi]

On Tue, Apr 30, 2024 at 01:09:59PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the EDP_PSR_AUX_CTL register macro.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Two things crossing my mind at this point:

1. perhaps we should have grouped by impacted file and all these psr cases
   together?
2. then perhaps while doing the whole file we could already do a
   s/dev_priv/i915 on those impacted functions..

but well, it crossed my mind, but I'm actually happy with this easy
review and perhaps a last full sed s/dev_priv/i915.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_psr.c      | 2 +-
>  drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 0b1f7e62470e..daeb1b65a2e5 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -323,7 +323,7 @@ static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv,
>  				  enum transcoder cpu_transcoder)
>  {
>  	if (DISPLAY_VER(dev_priv) >= 8)
> -		return EDP_PSR_AUX_CTL(cpu_transcoder);
> +		return EDP_PSR_AUX_CTL(dev_priv, cpu_transcoder);
>  	else
>  		return HSW_SRD_AUX_CTL;
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index 5fd4f875ade0..a4f785bcf605 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -86,7 +86,7 @@
>  #define HSW_SRD_AUX_CTL				_MMIO(0x64810)
>  #define _SRD_AUX_CTL_A				0x60810
>  #define _SRD_AUX_CTL_EDP			0x6f810
> -#define EDP_PSR_AUX_CTL(tran)			_MMIO_TRANS2(dev_priv, tran, _SRD_AUX_CTL_A)
> +#define EDP_PSR_AUX_CTL(dev_priv, tran)			_MMIO_TRANS2(dev_priv, tran, _SRD_AUX_CTL_A)
>  #define   EDP_PSR_AUX_CTL_TIME_OUT_MASK		DP_AUX_CH_CTL_TIME_OUT_MASK
>  #define   EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK	DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
>  #define   EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK	DP_AUX_CH_CTL_PRECHARGE_2US_MASK
> -- 
> 2.39.2
> 

Re: [PATCH 06/19] drm/i915: pass dev_priv explicitly to EDP_PSR_AUX_DATA

[Rodrigo Vivi]

On Tue, Apr 30, 2024 at 01:10:00PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the EDP_PSR_AUX_DATA register macro.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_psr.c      | 2 +-
>  drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index daeb1b65a2e5..5fe9feddc0e0 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -332,7 +332,7 @@ static i915_reg_t psr_aux_data_reg(struct drm_i915_private *dev_priv,
>  				   enum transcoder cpu_transcoder, int i)
>  {
>  	if (DISPLAY_VER(dev_priv) >= 8)
> -		return EDP_PSR_AUX_DATA(cpu_transcoder, i);
> +		return EDP_PSR_AUX_DATA(dev_priv, cpu_transcoder, i);
>  	else
>  		return HSW_SRD_AUX_DATA(i);
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index a4f785bcf605..6a6d7de901bc 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -96,7 +96,7 @@
>  #define HSW_SRD_AUX_DATA(i)			_MMIO(0x64814 + (i) * 4) /* 5 registers */
>  #define _SRD_AUX_DATA_A				0x60814
>  #define _SRD_AUX_DATA_EDP			0x6f814
> -#define EDP_PSR_AUX_DATA(tran, i)		_MMIO_TRANS2(dev_priv, tran, _SRD_AUX_DATA_A + (i) * 4) /* 5 registers */
> +#define EDP_PSR_AUX_DATA(dev_priv, tran, i)		_MMIO_TRANS2(dev_priv, tran, _SRD_AUX_DATA_A + (i) * 4) /* 5 registers */
>  
>  #define HSW_SRD_STATUS				_MMIO(0x64840)
>  #define _SRD_STATUS_A				0x60840
> -- 
> 2.39.2
> 

Re: [PATCH 07/19] drm/i915: pass dev_priv explicitly to EDP_PSR_STATUS

[Rodrigo Vivi]

On Tue, Apr 30, 2024 at 01:10:01PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the EDP_PSR_STATUS register macro.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_psr.c      | 2 +-
>  drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 5fe9feddc0e0..1a52a69e1906 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -296,7 +296,7 @@ static i915_reg_t psr_status_reg(struct drm_i915_private *dev_priv,
>  				 enum transcoder cpu_transcoder)
>  {
>  	if (DISPLAY_VER(dev_priv) >= 8)
> -		return EDP_PSR_STATUS(cpu_transcoder);
> +		return EDP_PSR_STATUS(dev_priv, cpu_transcoder);
>  	else
>  		return HSW_SRD_STATUS;
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index 6a6d7de901bc..4f3e58076a48 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -101,7 +101,7 @@
>  #define HSW_SRD_STATUS				_MMIO(0x64840)
>  #define _SRD_STATUS_A				0x60840
>  #define _SRD_STATUS_EDP				0x6f840
> -#define EDP_PSR_STATUS(tran)			_MMIO_TRANS2(dev_priv, tran, _SRD_STATUS_A)
> +#define EDP_PSR_STATUS(dev_priv, tran)			_MMIO_TRANS2(dev_priv, tran, _SRD_STATUS_A)
>  #define   EDP_PSR_STATUS_STATE_MASK		REG_GENMASK(31, 29)
>  #define   EDP_PSR_STATUS_STATE_IDLE		REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 0)
>  #define   EDP_PSR_STATUS_STATE_SRDONACK		REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 1)
> -- 
> 2.39.2
> 

Re: [PATCH 08/19] drm/i915: pass dev_priv explicitly to EDP_PSR_PERF_CNT

[Rodrigo Vivi]

On Tue, Apr 30, 2024 at 01:10:02PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the EDP_PSR_PERF_CNT register macro.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_psr.c      | 2 +-
>  drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 1a52a69e1906..162dd07c243f 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -287,7 +287,7 @@ static i915_reg_t psr_perf_cnt_reg(struct drm_i915_private *dev_priv,
>  				   enum transcoder cpu_transcoder)
>  {
>  	if (DISPLAY_VER(dev_priv) >= 8)
> -		return EDP_PSR_PERF_CNT(cpu_transcoder);
> +		return EDP_PSR_PERF_CNT(dev_priv, cpu_transcoder);
>  	else
>  		return HSW_SRD_PERF_CNT;
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index 4f3e58076a48..ef7f32c98d55 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -126,7 +126,7 @@
>  #define HSW_SRD_PERF_CNT		_MMIO(0x64844)
>  #define _SRD_PERF_CNT_A			0x60844
>  #define _SRD_PERF_CNT_EDP		0x6f844
> -#define EDP_PSR_PERF_CNT(tran)		_MMIO_TRANS2(dev_priv, tran, _SRD_PERF_CNT_A)
> +#define EDP_PSR_PERF_CNT(dev_priv, tran)		_MMIO_TRANS2(dev_priv, tran, _SRD_PERF_CNT_A)
>  #define   EDP_PSR_PERF_CNT_MASK		REG_GENMASK(23, 0)
>  
>  /* PSR_MASK on SKL+ */
> -- 
> 2.39.2
> 

Re: [PATCH 09/19] drm/i915: pass dev_priv explicitly to EDP_PSR_DEBUG

[Rodrigo Vivi]

On Tue, Apr 30, 2024 at 01:10:03PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the EDP_PSR_DEBUG register macro.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_psr.c      | 2 +-
>  drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 162dd07c243f..fa1fd04d3b4a 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -278,7 +278,7 @@ static i915_reg_t psr_debug_reg(struct drm_i915_private *dev_priv,
>  				enum transcoder cpu_transcoder)
>  {
>  	if (DISPLAY_VER(dev_priv) >= 8)
> -		return EDP_PSR_DEBUG(cpu_transcoder);
> +		return EDP_PSR_DEBUG(dev_priv, cpu_transcoder);
>  	else
>  		return HSW_SRD_DEBUG;
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index ef7f32c98d55..a74705aedbb5 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -133,7 +133,7 @@
>  #define HSW_SRD_DEBUG				_MMIO(0x64860)
>  #define _SRD_DEBUG_A				0x60860
>  #define _SRD_DEBUG_EDP				0x6f860
> -#define EDP_PSR_DEBUG(tran)			_MMIO_TRANS2(dev_priv, tran, _SRD_DEBUG_A)
> +#define EDP_PSR_DEBUG(dev_priv, tran)			_MMIO_TRANS2(dev_priv, tran, _SRD_DEBUG_A)
>  #define   EDP_PSR_DEBUG_MASK_MAX_SLEEP		REG_BIT(28)
>  #define   EDP_PSR_DEBUG_MASK_LPSP		REG_BIT(27)
>  #define   EDP_PSR_DEBUG_MASK_MEMUP		REG_BIT(26)
> -- 
> 2.39.2
> 

Re: [PATCH 10/19] drm/i915: pass dev_priv explicitly to EDP_PSR2_CTL

[Rodrigo Vivi]

On Tue, Apr 30, 2024 at 01:10:04PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the EDP_PSR2_CTL register macro.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_psr.c      | 15 +++++++++------
>  drivers/gpu/drm/i915/display/intel_psr_regs.h |  2 +-
>  2 files changed, 10 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index fa1fd04d3b4a..156660ab7adf 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -932,7 +932,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  	 */
>  	intel_de_write(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder), psr_val);
>  
> -	intel_de_write(dev_priv, EDP_PSR2_CTL(cpu_transcoder), val);
> +	intel_de_write(dev_priv, EDP_PSR2_CTL(dev_priv, cpu_transcoder), val);
>  }
>  
>  static bool
> @@ -963,7 +963,7 @@ static void psr2_program_idle_frames(struct intel_dp *intel_dp,
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
>  
> -	intel_de_rmw(dev_priv, EDP_PSR2_CTL(cpu_transcoder),
> +	intel_de_rmw(dev_priv, EDP_PSR2_CTL(dev_priv, cpu_transcoder),
>  		     EDP_PSR2_IDLE_FRAMES_MASK,
>  		     EDP_PSR2_IDLE_FRAMES(idle_frames));
>  }
> @@ -1700,7 +1700,7 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
>  
>  	drm_WARN_ON(&dev_priv->drm,
>  		    transcoder_has_psr2(dev_priv, cpu_transcoder) &&
> -		    intel_de_read(dev_priv, EDP_PSR2_CTL(cpu_transcoder)) & EDP_PSR2_ENABLE);
> +		    intel_de_read(dev_priv, EDP_PSR2_CTL(dev_priv, cpu_transcoder)) & EDP_PSR2_ENABLE);
>  
>  	drm_WARN_ON(&dev_priv->drm,
>  		    intel_de_read(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder)) & EDP_PSR_ENABLE);
> @@ -2011,7 +2011,8 @@ static void intel_psr_exit(struct intel_dp *intel_dp)
>  
>  	if (!intel_dp->psr.active) {
>  		if (transcoder_has_psr2(dev_priv, cpu_transcoder)) {
> -			val = intel_de_read(dev_priv, EDP_PSR2_CTL(cpu_transcoder));
> +			val = intel_de_read(dev_priv,
> +					    EDP_PSR2_CTL(dev_priv, cpu_transcoder));
>  			drm_WARN_ON(&dev_priv->drm, val & EDP_PSR2_ENABLE);
>  		}
>  
> @@ -2027,7 +2028,8 @@ static void intel_psr_exit(struct intel_dp *intel_dp)
>  	} else if (intel_dp->psr.psr2_enabled) {
>  		tgl_disallow_dc3co_on_psr2_exit(intel_dp);
>  
> -		val = intel_de_rmw(dev_priv, EDP_PSR2_CTL(cpu_transcoder),
> +		val = intel_de_rmw(dev_priv,
> +				   EDP_PSR2_CTL(dev_priv, cpu_transcoder),
>  				   EDP_PSR2_ENABLE, 0);
>  
>  		drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR2_ENABLE));
> @@ -3529,7 +3531,8 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
>  		val = intel_de_read(dev_priv, TRANS_DP2_CTL(cpu_transcoder));
>  		enabled = val & TRANS_DP2_PANEL_REPLAY_ENABLE;
>  	} else if (psr->psr2_enabled) {
> -		val = intel_de_read(dev_priv, EDP_PSR2_CTL(cpu_transcoder));
> +		val = intel_de_read(dev_priv,
> +				    EDP_PSR2_CTL(dev_priv, cpu_transcoder));
>  		enabled = val & EDP_PSR2_ENABLE;
>  	} else {
>  		val = intel_de_read(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder));
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index a74705aedbb5..785e4f9e7828 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -153,7 +153,7 @@
>  
>  #define _PSR2_CTL_A				0x60900
>  #define _PSR2_CTL_EDP				0x6f900
> -#define EDP_PSR2_CTL(tran)			_MMIO_TRANS2(dev_priv, tran, _PSR2_CTL_A)
> +#define EDP_PSR2_CTL(dev_priv, tran)			_MMIO_TRANS2(dev_priv, tran, _PSR2_CTL_A)
>  #define   EDP_PSR2_ENABLE			REG_BIT(31)
>  #define   EDP_SU_TRACK_ENABLE			REG_BIT(30) /* up to adl-p */
>  #define   TGL_EDP_PSR2_BLOCK_COUNT_MASK		REG_BIT(28)
> -- 
> 2.39.2
> 

Re: [PATCH 11/19] drm/i915: pass dev_priv explicitly to PSR_EVENT

[Rodrigo Vivi]

On Tue, Apr 30, 2024 at 01:10:05PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the PSR_EVENT register macro.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_psr.c      | 4 +++-
>  drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
>  2 files changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 156660ab7adf..2dca9957a06b 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -415,7 +415,9 @@ void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir)
>  		if (DISPLAY_VER(dev_priv) >= 9) {
>  			u32 val;
>  
> -			val = intel_de_rmw(dev_priv, PSR_EVENT(cpu_transcoder), 0, 0);
> +			val = intel_de_rmw(dev_priv,
> +					   PSR_EVENT(dev_priv, cpu_transcoder),
> +					   0, 0);
>  
>  			psr_event_print(dev_priv, val, intel_dp->psr.psr2_enabled);
>  		}
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index 785e4f9e7828..817bc372bf35 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -195,7 +195,7 @@
>  #define _PSR_EVENT_TRANS_C			0x62848
>  #define _PSR_EVENT_TRANS_D			0x63848
>  #define _PSR_EVENT_TRANS_EDP			0x6f848
> -#define PSR_EVENT(tran)				_MMIO_TRANS2(dev_priv, tran, _PSR_EVENT_TRANS_A)
> +#define PSR_EVENT(dev_priv, tran)				_MMIO_TRANS2(dev_priv, tran, _PSR_EVENT_TRANS_A)
>  #define  PSR_EVENT_PSR2_WD_TIMER_EXPIRE		REG_BIT(17)
>  #define  PSR_EVENT_PSR2_DISABLED		REG_BIT(16)
>  #define  PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN	REG_BIT(15)
> -- 
> 2.39.2
> 

Re: [PATCH 12/19] drm/i915: pass dev_priv explicitly to EDP_PSR2_STATUS

[Rodrigo Vivi]

On Tue, Apr 30, 2024 at 01:10:06PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the EDP_PSR2_STATUS register macro.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_psr.c      | 9 +++++----
>  drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
>  2 files changed, 6 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 2dca9957a06b..36c08cd3a624 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -2052,7 +2052,7 @@ static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp)
>  	u32 psr_status_mask;
>  
>  	if (intel_dp->psr.psr2_enabled) {
> -		psr_status = EDP_PSR2_STATUS(cpu_transcoder);
> +		psr_status = EDP_PSR2_STATUS(dev_priv, cpu_transcoder);
>  		psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
>  	} else {
>  		psr_status = psr_status_reg(dev_priv, cpu_transcoder);
> @@ -2768,7 +2768,7 @@ static int _psr2_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
>  	 * EDP_PSR2_STATUS_STATE_DEEP_SLEEP to be cleared.
>  	 */
>  	return intel_de_wait_for_clear(dev_priv,
> -				       EDP_PSR2_STATUS(cpu_transcoder),
> +				       EDP_PSR2_STATUS(dev_priv, cpu_transcoder),
>  				       EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 50);
>  }
>  
> @@ -2835,7 +2835,7 @@ static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp)
>  		return false;
>  
>  	if (intel_dp->psr.psr2_enabled) {
> -		reg = EDP_PSR2_STATUS(cpu_transcoder);
> +		reg = EDP_PSR2_STATUS(dev_priv, cpu_transcoder);
>  		mask = EDP_PSR2_STATUS_STATE_MASK;
>  	} else {
>  		reg = psr_status_reg(dev_priv, cpu_transcoder);
> @@ -3467,7 +3467,8 @@ psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
>  			"BUF_ON",
>  			"TG_ON"
>  		};
> -		val = intel_de_read(dev_priv, EDP_PSR2_STATUS(cpu_transcoder));
> +		val = intel_de_read(dev_priv,
> +				    EDP_PSR2_STATUS(dev_priv, cpu_transcoder));
>  		status_val = REG_FIELD_GET(EDP_PSR2_STATUS_STATE_MASK, val);
>  		if (status_val < ARRAY_SIZE(live_status))
>  			status = live_status[status_val];
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index 817bc372bf35..e6c62512512f 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -215,7 +215,7 @@
>  
>  #define _PSR2_STATUS_A				0x60940
>  #define _PSR2_STATUS_EDP			0x6f940
> -#define EDP_PSR2_STATUS(tran)			_MMIO_TRANS2(dev_priv, tran, _PSR2_STATUS_A)
> +#define EDP_PSR2_STATUS(dev_priv, tran)			_MMIO_TRANS2(dev_priv, tran, _PSR2_STATUS_A)
>  #define EDP_PSR2_STATUS_STATE_MASK		REG_GENMASK(31, 28)
>  #define EDP_PSR2_STATUS_STATE_DEEP_SLEEP	REG_FIELD_PREP(EDP_PSR2_STATUS_STATE_MASK, 0x8)
>  
> -- 
> 2.39.2
> 

Re: [PATCH 13/19] drm/i915: pass dev_priv explicitly to _PSR2_SU_STATUS

[Rodrigo Vivi]

On Tue, Apr 30, 2024 at 01:10:07PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the _PSR2_SU_STATUS register macro.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

why aren't we going one level up here already?

> ---
>  drivers/gpu/drm/i915/display/intel_psr_regs.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index e6c62512512f..762fc0ad7eb5 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -221,8 +221,8 @@
>  
>  #define _PSR2_SU_STATUS_A		0x60914
>  #define _PSR2_SU_STATUS_EDP		0x6f914
> -#define _PSR2_SU_STATUS(tran, index)	_MMIO_TRANS2(dev_priv, tran, _PSR2_SU_STATUS_A + (index) * 4)
> -#define PSR2_SU_STATUS(tran, frame)	(_PSR2_SU_STATUS(tran, (frame) / 3))
> +#define _PSR2_SU_STATUS(dev_priv, tran, index)	_MMIO_TRANS2(dev_priv, tran, _PSR2_SU_STATUS_A + (index) * 4)
> +#define PSR2_SU_STATUS(tran, frame)	(_PSR2_SU_STATUS(dev_priv, tran, (frame) / 3))
>  #define PSR2_SU_STATUS_SHIFT(frame)	(((frame) % 3) * 10)
>  #define PSR2_SU_STATUS_MASK(frame)	(0x3ff << PSR2_SU_STATUS_SHIFT(frame))
>  #define PSR2_SU_STATUS_FRAMES		8
> -- 
> 2.39.2
> 

Re: [PATCH 14/19] drm/i915: pass dev_priv explicitly to PSR2_MAN_TRK_CTL

[Rodrigo Vivi]

On Tue, Apr 30, 2024 at 01:10:08PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the PSR2_MAN_TRK_CTL register macro.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_psr.c      | 23 ++++++++++++-------
>  drivers/gpu/drm/i915/display/intel_psr_regs.h |  2 +-
>  2 files changed, 16 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 36c08cd3a624..ded7795e4c3a 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -844,7 +844,8 @@ static void dg2_activate_panel_replay(struct intel_dp *intel_dp)
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  
> -	intel_de_rmw(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
> +	intel_de_rmw(dev_priv,
> +		     PSR2_MAN_TRK_CTL(dev_priv, intel_dp->psr.transcoder),
>  		     0, ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME);
>  
>  	intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,
> @@ -919,10 +920,12 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  	if (intel_dp->psr.psr2_sel_fetch_enabled) {
>  		u32 tmp;
>  
> -		tmp = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(cpu_transcoder));
> +		tmp = intel_de_read(dev_priv,
> +				    PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder));
>  		drm_WARN_ON(&dev_priv->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE));
>  	} else if (HAS_PSR2_SEL_FETCH(dev_priv)) {
> -		intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(cpu_transcoder), 0);
> +		intel_de_write(dev_priv,
> +			       PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder), 0);
>  	}
>  
>  	if (psr2_su_region_et_valid(intel_dp))
> @@ -1681,7 +1684,8 @@ void intel_psr_get_config(struct intel_encoder *encoder,
>  		goto unlock;
>  
>  	if (HAS_PSR2_SEL_FETCH(dev_priv)) {
> -		val = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(cpu_transcoder));
> +		val = intel_de_read(dev_priv,
> +				    PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder));
>  		if (val & PSR2_MAN_TRK_CTL_ENABLE)
>  			pipe_config->enable_psr2_sel_fetch = true;
>  	}
> @@ -2251,7 +2255,7 @@ static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
>  
>  	if (intel_dp->psr.psr2_sel_fetch_enabled)
>  		intel_de_write(dev_priv,
> -			       PSR2_MAN_TRK_CTL(cpu_transcoder),
> +			       PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder),
>  			       man_trk_ctl_enable_bit_get(dev_priv) |
>  			       man_trk_ctl_partial_frame_bit_get(dev_priv) |
>  			       man_trk_ctl_single_full_frame_bit_get(dev_priv) |
> @@ -2293,7 +2297,7 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st
>  		break;
>  	}
>  
> -	intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(cpu_transcoder),
> +	intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder),
>  		       crtc_state->psr2_man_track_ctl);
>  
>  	if (!crtc_state->enable_psr2_su_region_et)
> @@ -3014,7 +3018,9 @@ static void _psr_invalidate_handle(struct intel_dp *intel_dp)
>  		val = man_trk_ctl_enable_bit_get(dev_priv) |
>  		      man_trk_ctl_partial_frame_bit_get(dev_priv) |
>  		      man_trk_ctl_continuos_full_frame(dev_priv);
> -		intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(cpu_transcoder), val);
> +		intel_de_write(dev_priv,
> +			       PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder),
> +			       val);
>  		intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
>  		intel_dp->psr.psr2_sel_fetch_cff_enabled = true;
>  	} else {
> @@ -3112,7 +3118,8 @@ static void _psr_flush_handle(struct intel_dp *intel_dp)
>  				 * SU configuration in case update is sent for any reason after
>  				 * sff bit gets cleared by the HW on next vblank.
>  				 */
> -				intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(cpu_transcoder),
> +				intel_de_write(dev_priv,
> +					       PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder),
>  					       val);
>  				intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
>  				intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index 762fc0ad7eb5..55e07e87dfbd 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -229,7 +229,7 @@
>  
>  #define _PSR2_MAN_TRK_CTL_A					0x60910
>  #define _PSR2_MAN_TRK_CTL_EDP					0x6f910
> -#define PSR2_MAN_TRK_CTL(tran)					_MMIO_TRANS2(dev_priv, tran, _PSR2_MAN_TRK_CTL_A)
> +#define PSR2_MAN_TRK_CTL(dev_priv, tran)					_MMIO_TRANS2(dev_priv, tran, _PSR2_MAN_TRK_CTL_A)
>  #define  PSR2_MAN_TRK_CTL_ENABLE				REG_BIT(31)
>  #define  PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK		REG_GENMASK(30, 21)
>  #define  PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)		REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
> -- 
> 2.39.2
> 

Re: [PATCH 15/19] drm/i915: pass dev_priv explicitly to PIPE_SRCSZ_ERLY_TPT

[Rodrigo Vivi]

On Tue, Apr 30, 2024 at 01:10:09PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the PIPE_SRCSZ_ERLY_TPT register macro.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cursor.c   | 2 +-
>  drivers/gpu/drm/i915/display/intel_psr.c      | 2 +-
>  drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
>  3 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
> index 23a122ee20c9..2118b87ccb10 100644
> --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> @@ -523,7 +523,7 @@ static void wa_16021440873(struct intel_plane *plane,
>  
>  	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), ctl);
>  
> -	intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(pipe),
> +	intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(dev_priv, pipe),
>  		       PIPESRC_HEIGHT(et_y_position));
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index ded7795e4c3a..37b85b721ddf 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -2303,7 +2303,7 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st
>  	if (!crtc_state->enable_psr2_su_region_et)
>  		return;
>  
> -	intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(crtc->pipe),
> +	intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(dev_priv, crtc->pipe),
>  		       crtc_state->pipe_srcsz_early_tpt);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index 55e07e87dfbd..4ccbb651016f 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -249,7 +249,7 @@
>  /* PSR2 Early transport */
>  #define _PIPE_SRCSZ_ERLY_TPT_A	0x70074
>  
> -#define PIPE_SRCSZ_ERLY_TPT(trans)	_MMIO_TRANS2(dev_priv, trans, _PIPE_SRCSZ_ERLY_TPT_A)
> +#define PIPE_SRCSZ_ERLY_TPT(dev_priv, trans)	_MMIO_TRANS2(dev_priv, trans, _PIPE_SRCSZ_ERLY_TPT_A)
>  
>  #define _SEL_FETCH_PLANE_BASE_1_A		0x70890
>  #define _SEL_FETCH_PLANE_BASE_2_A		0x708B0
> -- 
> 2.39.2
> 

Re: [PATCH 16/19] drm/i915: pass dev_priv explicitly to ALPM_CTL

[Rodrigo Vivi]

On Tue, Apr 30, 2024 at 01:10:10PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the ALPM_CTL register macro.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_psr.c      | 4 ++--
>  drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
>  2 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 37b85b721ddf..fad24b1e5ae2 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1812,7 +1812,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp)
>  
>  	alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(psr->alpm_parameters.check_entry_lines);
>  
> -	intel_de_write(dev_priv, ALPM_CTL(cpu_transcoder), alpm_ctl);
> +	intel_de_write(dev_priv, ALPM_CTL(dev_priv, cpu_transcoder), alpm_ctl);
>  }
>  
>  static void intel_psr_enable_source(struct intel_dp *intel_dp,
> @@ -2112,7 +2112,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
>  
>  	/* Panel Replay on eDP is always using ALPM aux less. */
>  	if (intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp)) {
> -		intel_de_rmw(dev_priv, ALPM_CTL(cpu_transcoder),
> +		intel_de_rmw(dev_priv, ALPM_CTL(dev_priv, cpu_transcoder),
>  			     ALPM_CTL_ALPM_ENABLE |
>  			     ALPM_CTL_ALPM_AUX_LESS_ENABLE, 0);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index 4ccbb651016f..4d950b22d4f1 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -297,7 +297,7 @@
>  						  _SEL_FETCH_PLANE_BASE_1_A)
>  
>  #define _ALPM_CTL_A	0x60950
> -#define ALPM_CTL(tran)	_MMIO_TRANS2(dev_priv, tran, _ALPM_CTL_A)
> +#define ALPM_CTL(dev_priv, tran)	_MMIO_TRANS2(dev_priv, tran, _ALPM_CTL_A)
>  #define  ALPM_CTL_ALPM_ENABLE				REG_BIT(31)
>  #define  ALPM_CTL_ALPM_AUX_LESS_ENABLE			REG_BIT(30)
>  #define  ALPM_CTL_LOBF_ENABLE				REG_BIT(29)
> -- 
> 2.39.2
> 

Re: [PATCH 17/19] drm/i915: pass dev_priv explicitly to ALPM_CTL2

[Rodrigo Vivi]

On Tue, Apr 30, 2024 at 01:10:11PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the ALPM_CTL2 register macro.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index 4d950b22d4f1..05dc1c1d4ac2 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -321,7 +321,7 @@
>  #define  ALPM_CTL_AUX_LESS_WAKE_TIME(val)		REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK, val)
>  
>  #define _ALPM_CTL2_A	0x60954
> -#define ALPM_CTL2(tran)	_MMIO_TRANS2(dev_priv, tran, _ALPM_CTL2_A)
> +#define ALPM_CTL2(dev_priv, tran)	_MMIO_TRANS2(dev_priv, tran, _ALPM_CTL2_A)

no usage? should we just delete it?

>  #define  ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK		REG_GENMASK(28, 24)
>  #define  ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY(val)		REG_FIELD_PREP(ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK, val)
>  #define  ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION_MASK		REG_GENMASK(19, 16)
> -- 
> 2.39.2
> 

Re: [PATCH 18/19] drm/i915: pass dev_priv explicitly to PORT_ALPM_CTL

[Rodrigo Vivi]

On Tue, Apr 30, 2024 at 01:10:12PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the PORT_ALPM_CTL register macro.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_psr.c      | 6 ++++--
>  drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
>  2 files changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index fad24b1e5ae2..e88f326b78d6 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1790,7 +1790,8 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp)
>  			ALPM_CTL_ALPM_AUX_LESS_ENABLE |
>  			ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS;
>  
> -		intel_de_write(dev_priv, PORT_ALPM_CTL(cpu_transcoder),
> +		intel_de_write(dev_priv,
> +			       PORT_ALPM_CTL(dev_priv, cpu_transcoder),
>  			       PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE |
>  			       PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) |
>  			       PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) |
> @@ -2116,7 +2117,8 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
>  			     ALPM_CTL_ALPM_ENABLE |
>  			     ALPM_CTL_ALPM_AUX_LESS_ENABLE, 0);
>  
> -		intel_de_rmw(dev_priv, PORT_ALPM_CTL(cpu_transcoder),
> +		intel_de_rmw(dev_priv,
> +			     PORT_ALPM_CTL(dev_priv, cpu_transcoder),
>  			     PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE, 0);
>  	}
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index 05dc1c1d4ac2..5e52dddacf91 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -335,7 +335,7 @@
>  #define  ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES(val)	REG_FIELD_PREP(ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES_MASK, val)
>  
>  #define _PORT_ALPM_CTL_A			0x16fa2c
> -#define PORT_ALPM_CTL(tran)			_MMIO_TRANS2(dev_priv, tran, _PORT_ALPM_CTL_A)
> +#define PORT_ALPM_CTL(dev_priv, tran)			_MMIO_TRANS2(dev_priv, tran, _PORT_ALPM_CTL_A)
>  #define  PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE	REG_BIT(31)
>  #define  PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK	REG_GENMASK(23, 20)
>  #define  PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(val)	REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK, val)
> -- 
> 2.39.2
> 

Re: [PATCH 19/19] drm/i915: pass dev_priv explicitly to PORT_ALPM_LFPS_CTL

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

On Tue, Apr 30, 2024 at 01:10:13PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the PORT_ALPM_LFPS_CTL register macro.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c      | 3 ++-
>  drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
>  2 files changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index e88f326b78d6..664ffda6a86d 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1798,7 +1798,8 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp)
>  			       PORT_ALPM_CTL_SILENCE_PERIOD(
>  				       psr->alpm_parameters.silence_period_sym_clocks));
>  
> -		intel_de_write(dev_priv, PORT_ALPM_LFPS_CTL(cpu_transcoder),
> +		intel_de_write(dev_priv,
> +			       PORT_ALPM_LFPS_CTL(dev_priv, cpu_transcoder),
>  			       PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) |
>  			       PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(
>  				       psr->alpm_parameters.lfps_half_cycle_num_of_syms) |
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index 5e52dddacf91..08c6d488e89d 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -345,7 +345,7 @@
>  #define  PORT_ALPM_CTL_SILENCE_PERIOD(val)	REG_FIELD_PREP(PORT_ALPM_CTL_SILENCE_PERIOD_MASK, val)
>  
>  #define _PORT_ALPM_LFPS_CTL_A					0x16fa30
> -#define PORT_ALPM_LFPS_CTL(tran)				_MMIO_TRANS2(dev_priv, tran, _PORT_ALPM_LFPS_CTL_A)
> +#define PORT_ALPM_LFPS_CTL(dev_priv, tran)				_MMIO_TRANS2(dev_priv, tran, _PORT_ALPM_LFPS_CTL_A)
>  #define  PORT_ALPM_LFPS_CTL_LFPS_START_POLARITY			REG_BIT(31)
>  #define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK		REG_GENMASK(27, 24)
>  #define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN		7
> -- 
> 2.39.2
> 

Re: [PATCH 05/19] drm/i915: pass dev_priv explicitly to EDP_PSR_AUX_CTL

[Jani Nikula]

On Tue, 30 Apr 2024, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> On Tue, Apr 30, 2024 at 01:09:59PM +0300, Jani Nikula wrote:
>> Avoid the implicit dev_priv local variable use, and pass dev_priv
>> explicitly to the EDP_PSR_AUX_CTL register macro.
>> 
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> Two things crossing my mind at this point:
>
> 1. perhaps we should have grouped by impacted file and all these psr cases
>    together?
> 2. then perhaps while doing the whole file we could already do a
>    s/dev_priv/i915 on those impacted functions..
>
> but well, it crossed my mind, but I'm actually happy with this easy
> review and perhaps a last full sed s/dev_priv/i915.

I'm actually not going for s/dev_priv/i915/ at all! The next step is
going to be passing struct intel_display * to the register macros. It'll
just work, because all they use is

#define DISPLAY_INFO(i915)		(__to_intel_display(i915)->info.__device_info)

which handles either.

And going for struct intel_display * is just slightly more involved than
the pure rename.

> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Thanks for the reviews!

BR,
Jani.

>
>> ---
>>  drivers/gpu/drm/i915/display/intel_psr.c      | 2 +-
>>  drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
>>  2 files changed, 2 insertions(+), 2 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>> index 0b1f7e62470e..daeb1b65a2e5 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> @@ -323,7 +323,7 @@ static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv,
>>  				  enum transcoder cpu_transcoder)
>>  {
>>  	if (DISPLAY_VER(dev_priv) >= 8)
>> -		return EDP_PSR_AUX_CTL(cpu_transcoder);
>> +		return EDP_PSR_AUX_CTL(dev_priv, cpu_transcoder);
>>  	else
>>  		return HSW_SRD_AUX_CTL;
>>  }
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
>> index 5fd4f875ade0..a4f785bcf605 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
>> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
>> @@ -86,7 +86,7 @@
>>  #define HSW_SRD_AUX_CTL				_MMIO(0x64810)
>>  #define _SRD_AUX_CTL_A				0x60810
>>  #define _SRD_AUX_CTL_EDP			0x6f810
>> -#define EDP_PSR_AUX_CTL(tran)			_MMIO_TRANS2(dev_priv, tran, _SRD_AUX_CTL_A)
>> +#define EDP_PSR_AUX_CTL(dev_priv, tran)			_MMIO_TRANS2(dev_priv, tran, _SRD_AUX_CTL_A)
>>  #define   EDP_PSR_AUX_CTL_TIME_OUT_MASK		DP_AUX_CH_CTL_TIME_OUT_MASK
>>  #define   EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK	DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
>>  #define   EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK	DP_AUX_CH_CTL_PRECHARGE_2US_MASK
>> -- 
>> 2.39.2
>> 

-- 
Jani Nikula, Intel

Re: [PATCH 13/19] drm/i915: pass dev_priv explicitly to _PSR2_SU_STATUS

[Jani Nikula]

On Tue, 30 Apr 2024, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> On Tue, Apr 30, 2024 at 01:10:07PM +0300, Jani Nikula wrote:
>> Avoid the implicit dev_priv local variable use, and pass dev_priv
>> explicitly to the _PSR2_SU_STATUS register macro.
>> 
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> why aren't we going one level up here already?

Oh, good catch. Because it's a dumb script. If I were to run the script
another time, it would spot that PSR2_SU_STATUS() now depends on
dev_priv, and would fix that in a separate commit.

I guess I'll do that and squash it here.

Thanks,
Jani.

>
>> ---
>>  drivers/gpu/drm/i915/display/intel_psr_regs.h | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
>> index e6c62512512f..762fc0ad7eb5 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
>> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
>> @@ -221,8 +221,8 @@
>>  
>>  #define _PSR2_SU_STATUS_A		0x60914
>>  #define _PSR2_SU_STATUS_EDP		0x6f914
>> -#define _PSR2_SU_STATUS(tran, index)	_MMIO_TRANS2(dev_priv, tran, _PSR2_SU_STATUS_A + (index) * 4)
>> -#define PSR2_SU_STATUS(tran, frame)	(_PSR2_SU_STATUS(tran, (frame) / 3))
>> +#define _PSR2_SU_STATUS(dev_priv, tran, index)	_MMIO_TRANS2(dev_priv, tran, _PSR2_SU_STATUS_A + (index) * 4)
>> +#define PSR2_SU_STATUS(tran, frame)	(_PSR2_SU_STATUS(dev_priv, tran, (frame) / 3))
>>  #define PSR2_SU_STATUS_SHIFT(frame)	(((frame) % 3) * 10)
>>  #define PSR2_SU_STATUS_MASK(frame)	(0x3ff << PSR2_SU_STATUS_SHIFT(frame))
>>  #define PSR2_SU_STATUS_FRAMES		8
>> -- 
>> 2.39.2
>> 

-- 
Jani Nikula, Intel

[PATCH v2] drm/i915: pass dev_priv explicitly to PSR2_SU_STATUS

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PSR2_SU_STATUS register macro.

v2: Expand from _PSR2_SU_STATUS to PSR2_SU_STATUS (Rodrigo)

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c      | 3 ++-
 drivers/gpu/drm/i915/display/intel_psr_regs.h | 4 ++--
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 36c08cd3a624..0412a2e1d638 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -3569,7 +3569,8 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
 		 * frame boundary between register reads
 		 */
 		for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame += 3) {
-			val = intel_de_read(dev_priv, PSR2_SU_STATUS(cpu_transcoder, frame));
+			val = intel_de_read(dev_priv,
+					    PSR2_SU_STATUS(dev_priv, cpu_transcoder, frame));
 			su_frames_val[frame / 3] = val;
 		}
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index e6c62512512f..5504593aa9d0 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -221,8 +221,8 @@
 
 #define _PSR2_SU_STATUS_A		0x60914
 #define _PSR2_SU_STATUS_EDP		0x6f914
-#define _PSR2_SU_STATUS(tran, index)	_MMIO_TRANS2(dev_priv, tran, _PSR2_SU_STATUS_A + (index) * 4)
-#define PSR2_SU_STATUS(tran, frame)	(_PSR2_SU_STATUS(tran, (frame) / 3))
+#define _PSR2_SU_STATUS(dev_priv, tran, index)	_MMIO_TRANS2(dev_priv, tran, _PSR2_SU_STATUS_A + (index) * 4)
+#define PSR2_SU_STATUS(dev_priv, tran, frame)	(_PSR2_SU_STATUS(dev_priv, tran, (frame) / 3))
 #define PSR2_SU_STATUS_SHIFT(frame)	(((frame) % 3) * 10)
 #define PSR2_SU_STATUS_MASK(frame)	(0x3ff << PSR2_SU_STATUS_SHIFT(frame))
 #define PSR2_SU_STATUS_FRAMES		8
-- 
2.39.2

Re: [PATCH 17/19] drm/i915: pass dev_priv explicitly to ALPM_CTL2

[Jani Nikula]

On Tue, 30 Apr 2024, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> On Tue, Apr 30, 2024 at 01:10:11PM +0300, Jani Nikula wrote:
>> Avoid the implicit dev_priv local variable use, and pass dev_priv
>> explicitly to the ALPM_CTL2 register macro.
>> 
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
>> index 4d950b22d4f1..05dc1c1d4ac2 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
>> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
>> @@ -321,7 +321,7 @@
>>  #define  ALPM_CTL_AUX_LESS_WAKE_TIME(val)		REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK, val)
>>  
>>  #define _ALPM_CTL2_A	0x60954
>> -#define ALPM_CTL2(tran)	_MMIO_TRANS2(dev_priv, tran, _ALPM_CTL2_A)
>> +#define ALPM_CTL2(dev_priv, tran)	_MMIO_TRANS2(dev_priv, tran, _ALPM_CTL2_A)
>
> no usage? should we just delete it?

I believe a recent addition to enable ALPM. Jouni?

BR,
Jani.

>
>>  #define  ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK		REG_GENMASK(28, 24)
>>  #define  ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY(val)		REG_FIELD_PREP(ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK, val)
>>  #define  ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION_MASK		REG_GENMASK(19, 16)
>> -- 
>> 2.39.2
>> 

-- 
Jani Nikula, Intel

✗ Fi.CI.CHECKPATCH: warning for drm/i915/psr: implicit dev_priv removal (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/psr: implicit dev_priv removal (rev2)
URL   : https://patchwork.freedesktop.org/series/133062/
State : warning

== Summary ==

Error: dim checkpatch failed
9f210da2f130 drm/i915: pass dev_priv explicitly to TRANS_EXITLINE
1c570d2b97e7 drm/i915: pass dev_priv explicitly to EDP_PSR_CTL
3c0a8df94ad0 drm/i915: pass dev_priv explicitly to TRANS_PSR_IMR
-:22: ERROR:CODE_INDENT: code indent should use tabs where possible
#22: FILE: drivers/gpu/drm/i915/display/intel_display_irq.c:1459:
+^I^I^I^I           TRANS_PSR_IMR(dev_priv, trans),$

-:22: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#22: FILE: drivers/gpu/drm/i915/display/intel_display_irq.c:1459:
+			intel_uncore_write(uncore,
+				           TRANS_PSR_IMR(dev_priv, trans),

-:23: ERROR:CODE_INDENT: code indent should use tabs where possible
#23: FILE: drivers/gpu/drm/i915/display/intel_display_irq.c:1460:
+^I^I^I^I           0xffffffff);$

total: 2 errors, 0 warnings, 1 checks, 26 lines checked
c789be39ac5c drm/i915: pass dev_priv explicitly to TRANS_PSR_IIR
-:22: ERROR:CODE_INDENT: code indent should use tabs where possible
#22: FILE: drivers/gpu/drm/i915/display/intel_display_irq.c:880:
+^I^I^I^I^I^I        intel_dp->psr.transcoder);$

-:22: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#22: FILE: drivers/gpu/drm/i915/display/intel_display_irq.c:880:
+				iir_reg = TRANS_PSR_IIR(dev_priv,
+						        intel_dp->psr.transcoder);

-:32: ERROR:CODE_INDENT: code indent should use tabs where possible
#32: FILE: drivers/gpu/drm/i915/display/intel_display_irq.c:1463:
+^I^I^I^I           TRANS_PSR_IIR(dev_priv, trans),$

-:32: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#32: FILE: drivers/gpu/drm/i915/display/intel_display_irq.c:1463:
+			intel_uncore_write(uncore,
+				           TRANS_PSR_IIR(dev_priv, trans),

-:33: ERROR:CODE_INDENT: code indent should use tabs where possible
#33: FILE: drivers/gpu/drm/i915/display/intel_display_irq.c:1464:
+^I^I^I^I           0xffffffff);$

total: 3 errors, 0 warnings, 2 checks, 44 lines checked
2c7b57873d75 drm/i915: pass dev_priv explicitly to EDP_PSR_AUX_CTL
b05f7c5f6f6d drm/i915: pass dev_priv explicitly to EDP_PSR_AUX_DATA
-:34: WARNING:LONG_LINE: line length of 129 exceeds 100 columns
#34: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:99:
+#define EDP_PSR_AUX_DATA(dev_priv, tran, i)		_MMIO_TRANS2(dev_priv, tran, _SRD_AUX_DATA_A + (i) * 4) /* 5 registers */

total: 0 errors, 1 warnings, 0 checks, 16 lines checked
7c973a714850 drm/i915: pass dev_priv explicitly to EDP_PSR_STATUS
64dff32c31ac drm/i915: pass dev_priv explicitly to EDP_PSR_PERF_CNT
-:34: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#34: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:129:
+#define EDP_PSR_PERF_CNT(dev_priv, tran)		_MMIO_TRANS2(dev_priv, tran, _SRD_PERF_CNT_A)

total: 0 errors, 1 warnings, 0 checks, 16 lines checked
67f16cf89fa5 drm/i915: pass dev_priv explicitly to EDP_PSR_DEBUG
2684ba34bd45 drm/i915: pass dev_priv explicitly to EDP_PSR2_CTL
-:39: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#39: FILE: drivers/gpu/drm/i915/display/intel_psr.c:1703:
+		    intel_de_read(dev_priv, EDP_PSR2_CTL(dev_priv, cpu_transcoder)) & EDP_PSR2_ENABLE);

total: 0 errors, 1 warnings, 0 checks, 59 lines checked
92798a0a4e88 drm/i915: pass dev_priv explicitly to PSR_EVENT
-:36: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#36: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:198:
+#define PSR_EVENT(dev_priv, tran)				_MMIO_TRANS2(dev_priv, tran, _PSR_EVENT_TRANS_A)

total: 0 errors, 1 warnings, 0 checks, 18 lines checked
72145c8d1ec4 drm/i915: pass dev_priv explicitly to EDP_PSR2_STATUS
a51fef53827a drm/i915: pass dev_priv explicitly to PSR2_SU_STATUS
-:37: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#37: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:224:
+#define _PSR2_SU_STATUS(dev_priv, tran, index)	_MMIO_TRANS2(dev_priv, tran, _PSR2_SU_STATUS_A + (index) * 4)

total: 0 errors, 1 warnings, 0 checks, 19 lines checked
7c977a95c8cd drm/i915: pass dev_priv explicitly to PSR2_MAN_TRK_CTL
-:99: WARNING:LONG_LINE: line length of 129 exceeds 100 columns
#99: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:232:
+#define PSR2_MAN_TRK_CTL(dev_priv, tran)					_MMIO_TRANS2(dev_priv, tran, _PSR2_MAN_TRK_CTL_A)

total: 0 errors, 1 warnings, 0 checks, 75 lines checked
e3caf76ccf07 drm/i915: pass dev_priv explicitly to PIPE_SRCSZ_ERLY_TPT
-:47: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#47: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:252:
+#define PIPE_SRCSZ_ERLY_TPT(dev_priv, trans)	_MMIO_TRANS2(dev_priv, trans, _PIPE_SRCSZ_ERLY_TPT_A)

total: 0 errors, 1 warnings, 0 checks, 24 lines checked
16f63422c5cf drm/i915: pass dev_priv explicitly to ALPM_CTL
1b304576f347 drm/i915: pass dev_priv explicitly to ALPM_CTL2
a20b448af521 drm/i915: pass dev_priv explicitly to PORT_ALPM_CTL
-:45: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#45: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:338:
+#define PORT_ALPM_CTL(dev_priv, tran)			_MMIO_TRANS2(dev_priv, tran, _PORT_ALPM_CTL_A)

total: 0 errors, 1 warnings, 0 checks, 26 lines checked
c78c00d14503 drm/i915: pass dev_priv explicitly to PORT_ALPM_LFPS_CTL
-:35: WARNING:LONG_LINE: line length of 123 exceeds 100 columns
#35: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:348:
+#define PORT_ALPM_LFPS_CTL(dev_priv, tran)				_MMIO_TRANS2(dev_priv, tran, _PORT_ALPM_LFPS_CTL_A)

total: 0 errors, 1 warnings, 0 checks, 17 lines checked

✗ Fi.CI.BAT: failure for drm/i915/psr: implicit dev_priv removal (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 8254 bytes --]

== Series Details ==

Series: drm/i915/psr: implicit dev_priv removal (rev2)
URL   : https://patchwork.freedesktop.org/series/133062/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_14691 -> Patchwork_133062v2
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_133062v2 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_133062v2, please notify your bug team ('I915-ci-infra@lists.freedesktop.org') to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v2/index.html

Participating hosts (38 -> 38)
------------------------------

  Additional (1): fi-kbl-8809g 
  Missing    (1): fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_133062v2:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live@workarounds:
    - fi-apl-guc:         [PASS][1] -> [DMESG-WARN][2] +4 other tests dmesg-warn
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14691/fi-apl-guc/igt@i915_selftest@live@workarounds.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v2/fi-apl-guc/igt@i915_selftest@live@workarounds.html

  
Known issues
------------

  Here are the changes found in Patchwork_133062v2 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@read_all_entries:
    - fi-apl-guc:         [PASS][3] -> [DMESG-WARN][4] ([i915#10900] / [i915#8585]) +5 other tests dmesg-warn
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14691/fi-apl-guc/igt@debugfs_test@read_all_entries.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v2/fi-apl-guc/igt@debugfs_test@read_all_entries.html

  * igt@gem_huc_copy@huc-copy:
    - fi-kbl-8809g:       NOTRUN -> [SKIP][5] ([i915#2190])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v2/fi-kbl-8809g/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@basic:
    - fi-kbl-8809g:       NOTRUN -> [SKIP][6] ([i915#4613]) +3 other tests skip
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v2/fi-kbl-8809g/igt@gem_lmem_swapping@basic.html

  * igt@i915_module_load@reload:
    - fi-apl-guc:         [PASS][7] -> [DMESG-WARN][8] ([i915#180] / [i915#1982] / [i915#8585])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14691/fi-apl-guc/igt@i915_module_load@reload.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v2/fi-apl-guc/igt@i915_module_load@reload.html

  * igt@i915_selftest@live@execlists:
    - fi-bsw-nick:        [PASS][9] -> [ABORT][10] ([i915#10594])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14691/fi-bsw-nick/igt@i915_selftest@live@execlists.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v2/fi-bsw-nick/igt@i915_selftest@live@execlists.html

  * igt@kms_addfb_basic@addfb25-4-tiled:
    - fi-apl-guc:         [PASS][11] -> [DMESG-WARN][12] ([i915#10900]) +35 other tests dmesg-warn
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14691/fi-apl-guc/igt@kms_addfb_basic@addfb25-4-tiled.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v2/fi-apl-guc/igt@kms_addfb_basic@addfb25-4-tiled.html

  * igt@kms_flip@basic-flip-vs-dpms@c-dp1:
    - fi-apl-guc:         [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +26 other tests dmesg-warn
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14691/fi-apl-guc/igt@kms_flip@basic-flip-vs-dpms@c-dp1.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v2/fi-apl-guc/igt@kms_flip@basic-flip-vs-dpms@c-dp1.html

  * igt@kms_flip@basic-flip-vs-wf_vblank@a-dp1:
    - fi-apl-guc:         [PASS][15] -> [DMESG-WARN][16] ([i915#180] / [i915#1982]) +1 other test dmesg-warn
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14691/fi-apl-guc/igt@kms_flip@basic-flip-vs-wf_vblank@a-dp1.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v2/fi-apl-guc/igt@kms_flip@basic-flip-vs-wf_vblank@a-dp1.html

  * igt@kms_force_connector_basic@force-load-detect:
    - fi-kbl-8809g:       NOTRUN -> [SKIP][17] +30 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v2/fi-kbl-8809g/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1:
    - fi-apl-guc:         [PASS][18] -> [DMESG-WARN][19] ([i915#180] / [i915#8585]) +7 other tests dmesg-warn
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14691/fi-apl-guc/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v2/fi-apl-guc/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1.html

  
#### Possible fixes ####

  * igt@gem_lmem_swapping@basic@lmem0:
    - bat-dg2-8:          [FAIL][20] ([i915#10378]) -> [PASS][21]
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14691/bat-dg2-8/igt@gem_lmem_swapping@basic@lmem0.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v2/bat-dg2-8/igt@gem_lmem_swapping@basic@lmem0.html

  * igt@i915_pm_rpm@module-reload:
    - {bat-mtlp-9}:       [CRASH][22] ([i915#10911]) -> [PASS][23]
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14691/bat-mtlp-9/igt@i915_pm_rpm@module-reload.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v2/bat-mtlp-9/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live@workarounds:
    - bat-arls-1:         [DMESG-FAIL][24] -> [PASS][25]
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14691/bat-arls-1/igt@i915_selftest@live@workarounds.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v2/bat-arls-1/igt@i915_selftest@live@workarounds.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
    - {bat-mtlp-9}:       [DMESG-WARN][26] ([i915#10435]) -> [PASS][27]
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14691/bat-mtlp-9/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v2/bat-mtlp-9/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html

  
#### Warnings ####

  * igt@i915_pm_rpm@module-reload:
    - fi-apl-guc:         [DMESG-WARN][28] ([i915#8585]) -> [DMESG-WARN][29] ([i915#180] / [i915#8585])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14691/fi-apl-guc/igt@i915_pm_rpm@module-reload.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v2/fi-apl-guc/igt@i915_pm_rpm@module-reload.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#10378]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10378
  [i915#10435]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10435
  [i915#10594]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10594
  [i915#10900]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10900
  [i915#10911]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10911
  [i915#180]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/180
  [i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
  [i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#8585]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8585


Build changes
-------------

  * Linux: CI_DRM_14691 -> Patchwork_133062v2

  CI-20190529: 20190529
  CI_DRM_14691: 0f511aa3b7d7eafc1f8d7cea4a29cc270b748212 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7828: 68a055ff91b91dadb01d9501cd8670f654b5b952 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_133062v2: 0f511aa3b7d7eafc1f8d7cea4a29cc270b748212 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133062v2/index.html

[-- Attachment #2: Type: text/html, Size: 10010 bytes --]

Re: [PATCH v2] drm/i915: pass dev_priv explicitly to PSR2_SU_STATUS

[Rodrigo Vivi]

On Thu, May 02, 2024 at 01:39:25PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the PSR2_SU_STATUS register macro.
> 
> v2: Expand from _PSR2_SU_STATUS to PSR2_SU_STATUS (Rodrigo)
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_psr.c      | 3 ++-
>  drivers/gpu/drm/i915/display/intel_psr_regs.h | 4 ++--
>  2 files changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 36c08cd3a624..0412a2e1d638 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -3569,7 +3569,8 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
>  		 * frame boundary between register reads
>  		 */
>  		for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame += 3) {
> -			val = intel_de_read(dev_priv, PSR2_SU_STATUS(cpu_transcoder, frame));
> +			val = intel_de_read(dev_priv,
> +					    PSR2_SU_STATUS(dev_priv, cpu_transcoder, frame));
>  			su_frames_val[frame / 3] = val;
>  		}
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index e6c62512512f..5504593aa9d0 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -221,8 +221,8 @@
>  
>  #define _PSR2_SU_STATUS_A		0x60914
>  #define _PSR2_SU_STATUS_EDP		0x6f914
> -#define _PSR2_SU_STATUS(tran, index)	_MMIO_TRANS2(dev_priv, tran, _PSR2_SU_STATUS_A + (index) * 4)
> -#define PSR2_SU_STATUS(tran, frame)	(_PSR2_SU_STATUS(tran, (frame) / 3))
> +#define _PSR2_SU_STATUS(dev_priv, tran, index)	_MMIO_TRANS2(dev_priv, tran, _PSR2_SU_STATUS_A + (index) * 4)
> +#define PSR2_SU_STATUS(dev_priv, tran, frame)	(_PSR2_SU_STATUS(dev_priv, tran, (frame) / 3))
>  #define PSR2_SU_STATUS_SHIFT(frame)	(((frame) % 3) * 10)
>  #define PSR2_SU_STATUS_MASK(frame)	(0x3ff << PSR2_SU_STATUS_SHIFT(frame))
>  #define PSR2_SU_STATUS_FRAMES		8
> -- 
> 2.39.2
> 

Re: [PATCH 05/19] drm/i915: pass dev_priv explicitly to EDP_PSR_AUX_CTL

[Rodrigo Vivi]

On Thu, May 02, 2024 at 12:28:33PM +0300, Jani Nikula wrote:
> On Tue, 30 Apr 2024, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> > On Tue, Apr 30, 2024 at 01:09:59PM +0300, Jani Nikula wrote:
> >> Avoid the implicit dev_priv local variable use, and pass dev_priv
> >> explicitly to the EDP_PSR_AUX_CTL register macro.
> >> 
> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >
> > Two things crossing my mind at this point:
> >
> > 1. perhaps we should have grouped by impacted file and all these psr cases
> >    together?
> > 2. then perhaps while doing the whole file we could already do a
> >    s/dev_priv/i915 on those impacted functions..
> >
> > but well, it crossed my mind, but I'm actually happy with this easy
> > review and perhaps a last full sed s/dev_priv/i915.
> 
> I'm actually not going for s/dev_priv/i915/ at all! The next step is
> going to be passing struct intel_display * to the register macros. It'll
> just work, because all they use is
> 
> #define DISPLAY_INFO(i915)		(__to_intel_display(i915)->info.__device_info)
> 
> which handles either.
> 
> And going for struct intel_display * is just slightly more involved than
> the pure rename.

ack. it makes total sense and much better indeed.

> 
> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> 
> Thanks for the reviews!
> 
> BR,
> Jani.
> 
> >
> >> ---
> >>  drivers/gpu/drm/i915/display/intel_psr.c      | 2 +-
> >>  drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
> >>  2 files changed, 2 insertions(+), 2 deletions(-)
> >> 
> >> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> >> index 0b1f7e62470e..daeb1b65a2e5 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> >> @@ -323,7 +323,7 @@ static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv,
> >>  				  enum transcoder cpu_transcoder)
> >>  {
> >>  	if (DISPLAY_VER(dev_priv) >= 8)
> >> -		return EDP_PSR_AUX_CTL(cpu_transcoder);
> >> +		return EDP_PSR_AUX_CTL(dev_priv, cpu_transcoder);
> >>  	else
> >>  		return HSW_SRD_AUX_CTL;
> >>  }
> >> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> >> index 5fd4f875ade0..a4f785bcf605 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> >> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> >> @@ -86,7 +86,7 @@
> >>  #define HSW_SRD_AUX_CTL				_MMIO(0x64810)
> >>  #define _SRD_AUX_CTL_A				0x60810
> >>  #define _SRD_AUX_CTL_EDP			0x6f810
> >> -#define EDP_PSR_AUX_CTL(tran)			_MMIO_TRANS2(dev_priv, tran, _SRD_AUX_CTL_A)
> >> +#define EDP_PSR_AUX_CTL(dev_priv, tran)			_MMIO_TRANS2(dev_priv, tran, _SRD_AUX_CTL_A)
> >>  #define   EDP_PSR_AUX_CTL_TIME_OUT_MASK		DP_AUX_CH_CTL_TIME_OUT_MASK
> >>  #define   EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK	DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
> >>  #define   EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK	DP_AUX_CH_CTL_PRECHARGE_2US_MASK
> >> -- 
> >> 2.39.2
> >> 
> 
> -- 
> Jani Nikula, Intel

Re: [PATCH 17/19] drm/i915: pass dev_priv explicitly to ALPM_CTL2

[Hogander, Jouni]

On Thu, 2024-05-02 at 13:40 +0300, Jani Nikula wrote:
> On Tue, 30 Apr 2024, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> > On Tue, Apr 30, 2024 at 01:10:11PM +0300, Jani Nikula wrote:
> > > Avoid the implicit dev_priv local variable use, and pass dev_priv
> > > explicitly to the ALPM_CTL2 register macro.
> > > 
> > > Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
> > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> > > b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> > > index 4d950b22d4f1..05dc1c1d4ac2 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> > > @@ -321,7 +321,7 @@
> > >  #define 
> > > ALPM_CTL_AUX_LESS_WAKE_TIME(val)              REG_FIELD_PREP(ALPM
> > > _CTL_AUX_LESS_WAKE_TIME_MASK, val)
> > >  
> > >  #define _ALPM_CTL2_A   0x60954
> > > -#define ALPM_CTL2(tran)        _MMIO_TRANS2(dev_priv, tran,
> > > _ALPM_CTL2_A)
> > > +#define ALPM_CTL2(dev_priv, tran)      _MMIO_TRANS2(dev_priv,
> > > tran, _ALPM_CTL2_A)
> > 
> > no usage? should we just delete it?
> 
> I believe a recent addition to enable ALPM. Jouni?

I added it together with other ALPM registers. Currently there is only
one field for LunarLake and we are not changing it from the default. I
would still keep it.

Reviewed-by: Jouni Högander <jouni.hogander@intel.com>


> 
> BR,
> Jani.
> 
> > 
> > >  #define 
> > > ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK               REG_GENMASK
> > > (28, 24)
> > >  #define 
> > > ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY(val)               REG_FIELD_P
> > > REP(ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK, val)
> > >  #define 
> > > ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION_MASK           REG_GENMASK
> > > (19, 16)
> > > -- 
> > > 2.39.2
> > > 
> 

Re: [PATCH 17/19] drm/i915: pass dev_priv explicitly to ALPM_CTL2

[Jani Nikula]

On Mon, 06 May 2024, "Hogander, Jouni" <jouni.hogander@intel.com> wrote:
> On Thu, 2024-05-02 at 13:40 +0300, Jani Nikula wrote:
>> On Tue, 30 Apr 2024, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
>> > On Tue, Apr 30, 2024 at 01:10:11PM +0300, Jani Nikula wrote:
>> > > Avoid the implicit dev_priv local variable use, and pass dev_priv
>> > > explicitly to the ALPM_CTL2 register macro.
>> > >
>> > > Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> > > ---
>> > >  drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
>> > >  1 file changed, 1 insertion(+), 1 deletion(-)
>> > >
>> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h
>> > > b/drivers/gpu/drm/i915/display/intel_psr_regs.h
>> > > index 4d950b22d4f1..05dc1c1d4ac2 100644
>> > > --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
>> > > +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
>> > > @@ -321,7 +321,7 @@
>> > >  #define
>> > > ALPM_CTL_AUX_LESS_WAKE_TIME(val)              REG_FIELD_PREP(ALPM
>> > > _CTL_AUX_LESS_WAKE_TIME_MASK, val)
>> > >
>> > >  #define _ALPM_CTL2_A   0x60954
>> > > -#define ALPM_CTL2(tran)        _MMIO_TRANS2(dev_priv, tran,
>> > > _ALPM_CTL2_A)
>> > > +#define ALPM_CTL2(dev_priv, tran)      _MMIO_TRANS2(dev_priv,
>> > > tran, _ALPM_CTL2_A)
>> >
>> > no usage? should we just delete it?
>>
>> I believe a recent addition to enable ALPM. Jouni?
>
> I added it together with other ALPM registers. Currently there is only
> one field for LunarLake and we are not changing it from the default. I
> would still keep it.
>
> Reviewed-by: Jouni Högander <jouni.hogander@intel.com>

Thanks for all the reviews, pushed the lot to drm-intel-next.

BR,
Jani.



>
>
>>
>> BR,
>> Jani.
>>
>> >
>> > >  #define
>> > > ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK               REG_GENMASK
>> > > (28, 24)
>> > >  #define
>> > > ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY(val)               REG_FIELD_P
>> > > REP(ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK, val)
>> > >  #define
>> > > ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION_MASK           REG_GENMASK
>> > > (19, 16)
>> > > --
>> > > 2.39.2
>> > >
>>
>

-- 
Jani Nikula, Intel