From: Charlie Jenkins <charlie@rivosinc.com>
To: Conor Dooley <conor@kernel.org>
Cc: "Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Guo Ren" <guoren@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Chen-Yu Tsai" <wens@csie.org>,
"Jernej Skrabec" <jernej.skrabec@gmail.com>,
"Samuel Holland" <samuel@sholland.org>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Evan Green" <evan@rivosinc.com>,
"Clément Léger" <cleger@rivosinc.com>,
"Jonathan Corbet" <corbet@lwn.net>,
"Shuah Khan" <shuah@kernel.org>,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
"Palmer Dabbelt" <palmer@rivosinc.com>,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org,
linux-kselftest@vger.kernel.org
Subject: Re: [PATCH v5 03/17] riscv: vector: Use vlenb from DT
Date: Fri, 3 May 2024 10:40:23 -0700 [thread overview]
Message-ID: <ZjUhh4tts6+0yfB/@ghost> (raw)
In-Reply-To: <20240503-reviver-unify-b07f33cb6053@spud>
On Fri, May 03, 2024 at 06:26:58PM +0100, Conor Dooley wrote:
> On Fri, May 03, 2024 at 10:15:16AM -0700, Charlie Jenkins wrote:
> > The DT is improperly
> > formatted since it has heterogeneous vlenb entries and has V enabled,
> > but since the user disabled V in the kernel skipping the warning is
> > reasonable.
>
> I wouldn't go as far as "improperly formatted", as if the harts really
> do have differing vector lengths, it's correctly formatted. It's just
> not something we support in Linux.
Fair enough, not supported is a better term here.
- Charlie
WARNING: multiple messages have this Message-ID (diff)
From: Charlie Jenkins <charlie@rivosinc.com>
To: Conor Dooley <conor@kernel.org>
Cc: "Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Guo Ren" <guoren@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Chen-Yu Tsai" <wens@csie.org>,
"Jernej Skrabec" <jernej.skrabec@gmail.com>,
"Samuel Holland" <samuel@sholland.org>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Evan Green" <evan@rivosinc.com>,
"Clément Léger" <cleger@rivosinc.com>,
"Jonathan Corbet" <corbet@lwn.net>,
"Shuah Khan" <shuah@kernel.org>,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
"Palmer Dabbelt" <palmer@rivosinc.com>,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org,
linux-kselftest@vger.kernel.org
Subject: Re: [PATCH v5 03/17] riscv: vector: Use vlenb from DT
Date: Fri, 3 May 2024 10:40:23 -0700 [thread overview]
Message-ID: <ZjUhh4tts6+0yfB/@ghost> (raw)
In-Reply-To: <20240503-reviver-unify-b07f33cb6053@spud>
On Fri, May 03, 2024 at 06:26:58PM +0100, Conor Dooley wrote:
> On Fri, May 03, 2024 at 10:15:16AM -0700, Charlie Jenkins wrote:
> > The DT is improperly
> > formatted since it has heterogeneous vlenb entries and has V enabled,
> > but since the user disabled V in the kernel skipping the warning is
> > reasonable.
>
> I wouldn't go as far as "improperly formatted", as if the harts really
> do have differing vector lengths, it's correctly formatted. It's just
> not something we support in Linux.
Fair enough, not supported is a better term here.
- Charlie
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Charlie Jenkins <charlie@rivosinc.com>
To: Conor Dooley <conor@kernel.org>
Cc: "Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Guo Ren" <guoren@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Chen-Yu Tsai" <wens@csie.org>,
"Jernej Skrabec" <jernej.skrabec@gmail.com>,
"Samuel Holland" <samuel@sholland.org>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Evan Green" <evan@rivosinc.com>,
"Clément Léger" <cleger@rivosinc.com>,
"Jonathan Corbet" <corbet@lwn.net>,
"Shuah Khan" <shuah@kernel.org>,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
"Palmer Dabbelt" <palmer@rivosinc.com>,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org,
linux-kselftest@vger.kernel.org
Subject: Re: [PATCH v5 03/17] riscv: vector: Use vlenb from DT
Date: Fri, 3 May 2024 10:40:23 -0700 [thread overview]
Message-ID: <ZjUhh4tts6+0yfB/@ghost> (raw)
In-Reply-To: <20240503-reviver-unify-b07f33cb6053@spud>
On Fri, May 03, 2024 at 06:26:58PM +0100, Conor Dooley wrote:
> On Fri, May 03, 2024 at 10:15:16AM -0700, Charlie Jenkins wrote:
> > The DT is improperly
> > formatted since it has heterogeneous vlenb entries and has V enabled,
> > but since the user disabled V in the kernel skipping the warning is
> > reasonable.
>
> I wouldn't go as far as "improperly formatted", as if the harts really
> do have differing vector lengths, it's correctly formatted. It's just
> not something we support in Linux.
Fair enough, not supported is a better term here.
- Charlie
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2024-05-03 17:40 UTC|newest]
Thread overview: 84+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-03 4:46 [PATCH v5 00/17] riscv: Support vendor extensions and xtheadvector Charlie Jenkins
2024-05-03 4:46 ` Charlie Jenkins
2024-05-03 4:46 ` Charlie Jenkins
2024-05-03 4:46 ` [PATCH v5 01/17] dt-bindings: riscv: Add xtheadvector ISA extension description Charlie Jenkins
2024-05-03 4:46 ` Charlie Jenkins
2024-05-03 4:46 ` Charlie Jenkins
2024-05-03 4:46 ` [PATCH v5 02/17] dt-bindings: riscv: cpus: add a vlen register length property Charlie Jenkins
2024-05-03 4:46 ` Charlie Jenkins
2024-05-03 4:46 ` Charlie Jenkins
2024-05-03 4:46 ` [PATCH v5 03/17] riscv: vector: Use vlenb from DT Charlie Jenkins
2024-05-03 4:46 ` Charlie Jenkins
2024-05-03 4:46 ` Charlie Jenkins
2024-05-03 16:59 ` Conor Dooley
2024-05-03 16:59 ` Conor Dooley
2024-05-03 16:59 ` Conor Dooley
2024-05-03 17:15 ` Charlie Jenkins
2024-05-03 17:15 ` Charlie Jenkins
2024-05-03 17:15 ` Charlie Jenkins
2024-05-03 17:26 ` Conor Dooley
2024-05-03 17:26 ` Conor Dooley
2024-05-03 17:26 ` Conor Dooley
2024-05-03 17:40 ` Charlie Jenkins [this message]
2024-05-03 17:40 ` Charlie Jenkins
2024-05-03 17:40 ` Charlie Jenkins
2024-05-03 4:46 ` [PATCH v5 04/17] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree Charlie Jenkins
2024-05-03 4:46 ` Charlie Jenkins
2024-05-03 4:46 ` Charlie Jenkins
2024-05-03 4:46 ` [PATCH v5 05/17] riscv: Extend cpufeature.c to detect vendor extensions Charlie Jenkins
2024-05-03 4:46 ` Charlie Jenkins
2024-05-03 4:46 ` Charlie Jenkins
2024-05-03 16:28 ` Evan Green
2024-05-03 16:28 ` Evan Green
2024-05-03 16:28 ` Evan Green
2024-05-03 17:08 ` Charlie Jenkins
2024-05-03 17:08 ` Charlie Jenkins
2024-05-03 17:08 ` Charlie Jenkins
2024-05-03 17:13 ` Evan Green
2024-05-03 17:13 ` Evan Green
2024-05-03 17:13 ` Evan Green
2024-05-03 17:38 ` Charlie Jenkins
2024-05-03 17:38 ` Charlie Jenkins
2024-05-03 17:38 ` Charlie Jenkins
2024-05-03 4:46 ` [PATCH v5 06/17] riscv: Add vendor extensions to /proc/cpuinfo Charlie Jenkins
2024-05-03 4:46 ` Charlie Jenkins
2024-05-03 4:46 ` Charlie Jenkins
2024-05-03 4:46 ` [PATCH v5 07/17] riscv: Introduce vendor variants of extension helpers Charlie Jenkins
2024-05-03 4:46 ` Charlie Jenkins
2024-05-03 4:46 ` Charlie Jenkins
2024-05-03 4:46 ` [PATCH v5 08/17] riscv: cpufeature: Extract common elements from extension checking Charlie Jenkins
2024-05-03 4:46 ` Charlie Jenkins
2024-05-03 4:46 ` Charlie Jenkins
2024-05-03 4:46 ` [PATCH v5 09/17] riscv: Convert xandespmu to use the vendor extension framework Charlie Jenkins
2024-05-03 4:46 ` Charlie Jenkins
2024-05-03 4:46 ` Charlie Jenkins
2024-05-03 4:46 ` [PATCH v5 10/17] RISC-V: define the elements of the VCSR vector CSR Charlie Jenkins
2024-05-03 4:46 ` Charlie Jenkins
2024-05-03 4:46 ` Charlie Jenkins
2024-05-03 4:46 ` [PATCH v5 11/17] riscv: csr: Add CSR encodings for VCSR_VXRM/VCSR_VXSAT Charlie Jenkins
2024-05-03 4:46 ` Charlie Jenkins
2024-05-03 4:46 ` Charlie Jenkins
2024-05-03 4:46 ` [PATCH v5 12/17] riscv: Add xtheadvector instruction definitions Charlie Jenkins
2024-05-03 4:46 ` Charlie Jenkins
2024-05-03 4:46 ` Charlie Jenkins
2024-05-03 4:46 ` [PATCH v5 13/17] riscv: vector: Support xtheadvector save/restore Charlie Jenkins
2024-05-03 4:46 ` Charlie Jenkins
2024-05-03 4:46 ` Charlie Jenkins
2024-05-03 4:46 ` [PATCH v5 14/17] riscv: hwprobe: Add thead vendor extension probing Charlie Jenkins
2024-05-03 4:46 ` Charlie Jenkins
2024-05-03 4:46 ` Charlie Jenkins
2024-05-03 16:29 ` Evan Green
2024-05-03 16:29 ` Evan Green
2024-05-03 16:29 ` Evan Green
2024-05-03 4:46 ` [PATCH v5 15/17] riscv: hwprobe: Document thead vendor extensions and xtheadvector extension Charlie Jenkins
2024-05-03 4:46 ` Charlie Jenkins
2024-05-03 4:46 ` Charlie Jenkins
2024-05-03 16:29 ` Evan Green
2024-05-03 16:29 ` Evan Green
2024-05-03 16:29 ` Evan Green
2024-05-03 4:46 ` [PATCH v5 16/17] selftests: riscv: Fix vector tests Charlie Jenkins
2024-05-03 4:46 ` Charlie Jenkins
2024-05-03 4:46 ` Charlie Jenkins
2024-05-03 4:46 ` [PATCH v5 17/17] selftests: riscv: Support xtheadvector in " Charlie Jenkins
2024-05-03 4:46 ` Charlie Jenkins
2024-05-03 4:46 ` Charlie Jenkins
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