Re: [PATCH v8 02/14] iommu/arm-smmu-v3: Start building a generic PASID layer

From: Nicolin Chen <nicolinc@nvidia.com>
To: Jason Gunthorpe <jgg@nvidia.com>
Cc: <iommu@lists.linux.dev>, Joerg Roedel <joro@8bytes.org>,
	<linux-arm-kernel@lists.infradead.org>,
	Robin Murphy <robin.murphy@arm.com>,
	Will Deacon <will@kernel.org>, Eric Auger <eric.auger@redhat.com>,
	Jean-Philippe Brucker <jean-philippe@linaro.org>,
	Moritz Fischer <mdf@kernel.org>,
	Michael Shavit <mshavit@google.com>, <patches@lists.linux.dev>,
	Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>
Subject: Re: [PATCH v8 02/14] iommu/arm-smmu-v3: Start building a generic PASID layer
Date: Mon, 3 Jun 2024 22:07:11 -0700	[thread overview]
Message-ID: <Zl6g/6Dz4il+bpU8@Asurada-Nvidia> (raw)
In-Reply-To: <2-v8-6f85cdc10ce7+563e-smmuv3_newapi_p2b_jgg@nvidia.com>

On Mon, Jun 03, 2024 at 09:15:47PM -0300, Jason Gunthorpe wrote:
> Add arm_smmu_set_pasid()/arm_smmu_remove_pasid() which are to be used by
> callers that already constructed the arm_smmu_cd they wish to program.
> 
> These functions will encapsulate the shared logic to setup a CD entry that
> will be shared by SVA and S1 domain cases.
> 
> Prior fixes had already moved most of this logic up into
> __arm_smmu_sva_bind(), move it to it's final home.
> 
> Following patches will relieve some of the remaining SVA restrictions:
> 
>  - The RID domain is a S1 domain and has already setup the STE to point to
>    the CD table
>  - The programmed PASID is the mm_get_enqcmd_pasid()
>  - Nothing changes while SVA is running (sva_enable)
> 
> SVA invalidation will still iterate over the S1 domain's master list,
> later patches will resolve that.
> 
> Tested-by: Nicolin Chen <nicolinc@nvidia.com>
> Tested-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>

Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>