From: "Roger Pau Monné" <roger.pau@citrix.com>
To: Julien Grall <julien@xen.org>
Cc: Stewart Hildebrand <stewart.hildebrand@amd.com>,
xen-devel@lists.xenproject.org,
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com>,
Stefano Stabellini <sstabellini@kernel.org>,
Bertrand Marquis <bertrand.marquis@arm.com>,
Michal Orzel <michal.orzel@amd.com>
Subject: Re: [PATCH v16 1/5] arm/vpci: honor access size when returning an error
Date: Tue, 28 May 2024 09:11:56 +0200 [thread overview]
Message-ID: <ZlWDvJ9_Om_3gX3b@macbook> (raw)
In-Reply-To: <3b3fd3a2-6b5c-41a2-a0b3-219a362f645f@xen.org>
On Mon, May 27, 2024 at 10:14:59PM +0100, Julien Grall wrote:
> Hi Roger,
>
> On 23/05/2024 08:55, Roger Pau Monné wrote:
> > On Wed, May 22, 2024 at 06:59:20PM -0400, Stewart Hildebrand wrote:
> > > From: Volodymyr Babchuk <Volodymyr_Babchuk@epam.com>
> > >
> > > Guest can try to read config space using different access sizes: 8,
> > > 16, 32, 64 bits. We need to take this into account when we are
> > > returning an error back to MMIO handler, otherwise it is possible to
> > > provide more data than requested: i.e. guest issues LDRB instruction
> > > to read one byte, but we are writing 0xFFFFFFFFFFFFFFFF in the target
> > > register.
> >
> > Shouldn't this be taken care of in the trap handler subsystem, rather
> > than forcing each handler to ensure the returned data matches the
> > access size?
>
> I understand how this can be useful when we return all 1s.
>
> However, in most of the current cases, we already need to deal with the
> masking because the data is extracted from a wider field (for instance, see
> the vGIC emulation). For those handlers, I would argue it would be
> concerning/ a bug if the handler return bits above the access size.
> Although, this would only impact the guest itself.
Even if there was a bug in the handler, it would be mitigated by the
truncation done in io.c.
> So overall, this seems to be a matter of taste and I don't quite (yet) see
> the benefits to do it in io.c. Regardless that...
It's up to you really, it's all ARM code so I don't really have a
stake. IMO it makes the handlers more complicated and fragile.
If nothing else I would at least add an ASSERT() in io.c to ensure
that the data returned from the handler matches the size constrains
you expect.
> >
> > IOW, something like:
> >
> > diff --git a/xen/arch/arm/io.c b/xen/arch/arm/io.c
> > index 96c740d5636c..b7e12df85f87 100644
> > --- a/xen/arch/arm/io.c
> > +++ b/xen/arch/arm/io.c
> > @@ -37,6 +37,7 @@ static enum io_state handle_read(const struct mmio_handler *handler,
> > return IO_ABORT;
> >
> > r = sign_extend(dabt, r);
> > + r = r & GENMASK_ULL((1U << dabt.size) * 8 - 1, 0);
>
> ... in some case we need to sign extend up to the width of the register
> (even if the access is 8-byte). So we would need to do the masking *before*
> calling sign_extend().
I would consider doing the truncation in sign_extend() if suitable,
even if that's doing more than what the function name implies.
Thanks, Roger.
next prev parent reply other threads:[~2024-05-28 7:12 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-22 22:59 [PATCH v16 0/5] PCI devices passthrough on Arm, part 3 Stewart Hildebrand
2024-05-22 22:59 ` [PATCH v16 1/5] arm/vpci: honor access size when returning an error Stewart Hildebrand
2024-05-22 23:04 ` Stewart Hildebrand
2024-05-23 7:55 ` Roger Pau Monné
2024-05-27 21:14 ` Julien Grall
2024-05-28 7:11 ` Roger Pau Monné [this message]
2024-05-28 9:18 ` Julien Grall
2024-05-22 22:59 ` [PATCH v16 2/5] vpci/header: emulate PCI_COMMAND register for guests Stewart Hildebrand
2024-05-22 22:59 ` [PATCH v16 3/5] vpci: add initial support for virtual PCI bus topology Stewart Hildebrand
2024-05-23 7:30 ` Roger Pau Monné
2024-05-22 22:59 ` [PATCH v16 4/5] xen/arm: translate virtual PCI bus topology for guests Stewart Hildebrand
2024-05-23 7:48 ` Roger Pau Monné
2024-05-24 13:21 ` Julien Grall
2024-05-27 7:45 ` Roger Pau Monné
2025-03-06 19:36 ` Stewart Hildebrand
2024-05-22 22:59 ` [PATCH v16 5/5] xen/arm: account IO handlers for emulated PCI MSI-X Stewart Hildebrand
2024-05-23 7:59 ` Roger Pau Monné
2025-02-28 14:40 ` [PATCH v16 0/5] PCI devices passthrough on Arm, part 3 Mykyta Poturai
2025-03-02 16:01 ` Stewart Hildebrand
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