From: Charlie Jenkins <charlie@rivosinc.com>
To: kvm-riscv@lists.infradead.org
Subject: [PATCH v5 03/16] riscv: hwprobe: export Zimop ISA extension
Date: Wed, 29 May 2024 15:11:03 -0700 [thread overview]
Message-ID: <Zlen931jkx9zGthc@ghost> (raw)
In-Reply-To: <20240517145302.971019-4-cleger@rivosinc.com>
On Fri, May 17, 2024 at 04:52:43PM +0200, Cl?ment L?ger wrote:
> Export Zimop ISA extension through hwprobe.
>
> Signed-off-by: Cl?ment L?ger <cleger@rivosinc.com>
> ---
> Documentation/arch/riscv/hwprobe.rst | 4 ++++
> arch/riscv/include/uapi/asm/hwprobe.h | 1 +
> arch/riscv/kernel/sys_hwprobe.c | 1 +
> 3 files changed, 6 insertions(+)
>
> diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
> index 204cd4433af5..48be38e0b788 100644
> --- a/Documentation/arch/riscv/hwprobe.rst
> +++ b/Documentation/arch/riscv/hwprobe.rst
> @@ -192,6 +192,10 @@ The following keys are defined:
> supported as defined in the RISC-V ISA manual starting from commit
> d8ab5c78c207 ("Zihintpause is ratified").
>
> + * :c:macro:`RISCV_HWPROBE_EXT_ZIMOP`: The Zimop May-Be-Operations extension is
> + supported as defined in the RISC-V ISA manual starting from commit
> + 58220614a5f ("Zimop is ratified/1.0").
> +
> * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
> information about the selected set of processors.
>
> diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> index 31c570cbd1c5..3b16a12204b1 100644
> --- a/arch/riscv/include/uapi/asm/hwprobe.h
> +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> @@ -60,6 +60,7 @@ struct riscv_hwprobe {
> #define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34)
> #define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35)
> #define RISCV_HWPROBE_EXT_ZIHINTPAUSE (1ULL << 36)
> +#define RISCV_HWPROBE_EXT_ZIMOP (1ULL << 37)
> #define RISCV_HWPROBE_KEY_CPUPERF_0 5
> #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
> #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
> diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
> index 969ef3d59dbe..fc6f4238f0b3 100644
> --- a/arch/riscv/kernel/sys_hwprobe.c
> +++ b/arch/riscv/kernel/sys_hwprobe.c
> @@ -112,6 +112,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
> EXT_KEY(ZACAS);
> EXT_KEY(ZICOND);
> EXT_KEY(ZIHINTPAUSE);
> + EXT_KEY(ZIMOP);
>
> if (has_vector()) {
> EXT_KEY(ZVBB);
> --
> 2.43.0
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
WARNING: multiple messages have this Message-ID (diff)
From: Charlie Jenkins <charlie@rivosinc.com>
To: "Clément Léger" <cleger@rivosinc.com>
Cc: Jonathan Corbet <corbet@lwn.net>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Conor Dooley <conor@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Anup Patel <anup@brainfault.org>, Shuah Khan <shuah@kernel.org>,
Atish Patra <atishp@atishpatra.org>,
linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-kselftest@vger.kernel.org
Subject: Re: [PATCH v5 03/16] riscv: hwprobe: export Zimop ISA extension
Date: Wed, 29 May 2024 15:11:03 -0700 [thread overview]
Message-ID: <Zlen931jkx9zGthc@ghost> (raw)
In-Reply-To: <20240517145302.971019-4-cleger@rivosinc.com>
On Fri, May 17, 2024 at 04:52:43PM +0200, Clément Léger wrote:
> Export Zimop ISA extension through hwprobe.
>
> Signed-off-by: Clément Léger <cleger@rivosinc.com>
> ---
> Documentation/arch/riscv/hwprobe.rst | 4 ++++
> arch/riscv/include/uapi/asm/hwprobe.h | 1 +
> arch/riscv/kernel/sys_hwprobe.c | 1 +
> 3 files changed, 6 insertions(+)
>
> diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
> index 204cd4433af5..48be38e0b788 100644
> --- a/Documentation/arch/riscv/hwprobe.rst
> +++ b/Documentation/arch/riscv/hwprobe.rst
> @@ -192,6 +192,10 @@ The following keys are defined:
> supported as defined in the RISC-V ISA manual starting from commit
> d8ab5c78c207 ("Zihintpause is ratified").
>
> + * :c:macro:`RISCV_HWPROBE_EXT_ZIMOP`: The Zimop May-Be-Operations extension is
> + supported as defined in the RISC-V ISA manual starting from commit
> + 58220614a5f ("Zimop is ratified/1.0").
> +
> * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
> information about the selected set of processors.
>
> diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> index 31c570cbd1c5..3b16a12204b1 100644
> --- a/arch/riscv/include/uapi/asm/hwprobe.h
> +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> @@ -60,6 +60,7 @@ struct riscv_hwprobe {
> #define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34)
> #define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35)
> #define RISCV_HWPROBE_EXT_ZIHINTPAUSE (1ULL << 36)
> +#define RISCV_HWPROBE_EXT_ZIMOP (1ULL << 37)
> #define RISCV_HWPROBE_KEY_CPUPERF_0 5
> #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
> #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
> diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
> index 969ef3d59dbe..fc6f4238f0b3 100644
> --- a/arch/riscv/kernel/sys_hwprobe.c
> +++ b/arch/riscv/kernel/sys_hwprobe.c
> @@ -112,6 +112,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
> EXT_KEY(ZACAS);
> EXT_KEY(ZICOND);
> EXT_KEY(ZIHINTPAUSE);
> + EXT_KEY(ZIMOP);
>
> if (has_vector()) {
> EXT_KEY(ZVBB);
> --
> 2.43.0
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
WARNING: multiple messages have this Message-ID (diff)
From: Charlie Jenkins <charlie@rivosinc.com>
To: "Clément Léger" <cleger@rivosinc.com>
Cc: Jonathan Corbet <corbet@lwn.net>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Conor Dooley <conor@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Anup Patel <anup@brainfault.org>, Shuah Khan <shuah@kernel.org>,
Atish Patra <atishp@atishpatra.org>,
linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-kselftest@vger.kernel.org
Subject: Re: [PATCH v5 03/16] riscv: hwprobe: export Zimop ISA extension
Date: Wed, 29 May 2024 15:11:03 -0700 [thread overview]
Message-ID: <Zlen931jkx9zGthc@ghost> (raw)
In-Reply-To: <20240517145302.971019-4-cleger@rivosinc.com>
On Fri, May 17, 2024 at 04:52:43PM +0200, Clément Léger wrote:
> Export Zimop ISA extension through hwprobe.
>
> Signed-off-by: Clément Léger <cleger@rivosinc.com>
> ---
> Documentation/arch/riscv/hwprobe.rst | 4 ++++
> arch/riscv/include/uapi/asm/hwprobe.h | 1 +
> arch/riscv/kernel/sys_hwprobe.c | 1 +
> 3 files changed, 6 insertions(+)
>
> diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
> index 204cd4433af5..48be38e0b788 100644
> --- a/Documentation/arch/riscv/hwprobe.rst
> +++ b/Documentation/arch/riscv/hwprobe.rst
> @@ -192,6 +192,10 @@ The following keys are defined:
> supported as defined in the RISC-V ISA manual starting from commit
> d8ab5c78c207 ("Zihintpause is ratified").
>
> + * :c:macro:`RISCV_HWPROBE_EXT_ZIMOP`: The Zimop May-Be-Operations extension is
> + supported as defined in the RISC-V ISA manual starting from commit
> + 58220614a5f ("Zimop is ratified/1.0").
> +
> * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
> information about the selected set of processors.
>
> diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> index 31c570cbd1c5..3b16a12204b1 100644
> --- a/arch/riscv/include/uapi/asm/hwprobe.h
> +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> @@ -60,6 +60,7 @@ struct riscv_hwprobe {
> #define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34)
> #define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35)
> #define RISCV_HWPROBE_EXT_ZIHINTPAUSE (1ULL << 36)
> +#define RISCV_HWPROBE_EXT_ZIMOP (1ULL << 37)
> #define RISCV_HWPROBE_KEY_CPUPERF_0 5
> #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
> #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
> diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
> index 969ef3d59dbe..fc6f4238f0b3 100644
> --- a/arch/riscv/kernel/sys_hwprobe.c
> +++ b/arch/riscv/kernel/sys_hwprobe.c
> @@ -112,6 +112,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
> EXT_KEY(ZACAS);
> EXT_KEY(ZICOND);
> EXT_KEY(ZIHINTPAUSE);
> + EXT_KEY(ZIMOP);
>
> if (has_vector()) {
> EXT_KEY(ZVBB);
> --
> 2.43.0
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2024-05-29 22:11 UTC|newest]
Thread overview: 108+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-17 14:52 [PATCH v5 00/16] Add support for a few Zc* extensions, Zcmop and Zimop Clément Léger
2024-05-17 14:52 ` Clément Léger
2024-05-17 14:52 ` Clément Léger
2024-05-17 14:52 ` [PATCH v5 01/16] dt-bindings: riscv: add Zimop ISA extension description Clément Léger
2024-05-17 14:52 ` Clément Léger
2024-05-17 14:52 ` Clément Léger
2024-05-29 22:10 ` Charlie Jenkins
2024-05-29 22:10 ` Charlie Jenkins
2024-05-29 22:10 ` Charlie Jenkins
2024-05-17 14:52 ` [PATCH v5 02/16] riscv: add ISA extension parsing for Zimop Clément Léger
2024-05-17 14:52 ` Clément Léger
2024-05-17 14:52 ` Clément Léger
2024-05-29 22:08 ` Charlie Jenkins
2024-05-29 22:08 ` Charlie Jenkins
2024-05-29 22:08 ` Charlie Jenkins
2024-05-29 22:21 ` Charlie Jenkins
2024-05-29 22:21 ` Charlie Jenkins
2024-05-29 22:21 ` Charlie Jenkins
2024-05-30 8:12 ` Clément Léger
2024-05-30 8:12 ` Clément Léger
2024-05-30 8:12 ` Clément Léger
2024-05-30 14:37 ` Charlie Jenkins
2024-05-30 14:37 ` Charlie Jenkins
2024-05-30 14:37 ` Charlie Jenkins
2024-05-30 14:38 ` Clément Léger
2024-05-30 14:38 ` Clément Léger
2024-05-30 14:38 ` Clément Léger
2024-05-17 14:52 ` [PATCH v5 03/16] riscv: hwprobe: export Zimop ISA extension Clément Léger
2024-05-17 14:52 ` Clément Léger
2024-05-17 14:52 ` Clément Léger
2024-05-29 22:11 ` Charlie Jenkins [this message]
2024-05-29 22:11 ` Charlie Jenkins
2024-05-29 22:11 ` Charlie Jenkins
2024-05-17 14:52 ` [PATCH v5 04/16] RISC-V: KVM: Allow Zimop extension for Guest/VM Clément Léger
2024-05-17 14:52 ` Clément Léger
2024-05-17 14:52 ` Clément Léger
2024-05-17 15:17 ` Anup Patel
2024-05-17 15:17 ` Anup Patel
2024-05-17 15:17 ` Anup Patel
2024-05-29 22:16 ` Charlie Jenkins
2024-05-29 22:16 ` Charlie Jenkins
2024-05-29 22:16 ` Charlie Jenkins
2024-05-17 14:52 ` [PATCH v5 05/16] KVM: riscv: selftests: Add Zimop extension to get-reg-list test Clément Léger
2024-05-17 14:52 ` Clément Léger
2024-05-17 14:52 ` Clément Léger
2024-05-17 15:18 ` Anup Patel
2024-05-17 15:18 ` Anup Patel
2024-05-17 15:18 ` Anup Patel
2024-05-17 14:52 ` [PATCH v5 06/16] dt-bindings: riscv: add Zca, Zcf, Zcd and Zcb ISA extension description Clément Léger
2024-05-17 14:52 ` Clément Léger
2024-05-17 14:52 ` Clément Léger
2024-05-29 22:13 ` Charlie Jenkins
2024-05-29 22:13 ` Charlie Jenkins
2024-05-29 22:13 ` Charlie Jenkins
2024-05-17 14:52 ` [PATCH v5 07/16] riscv: add ISA extensions validation callback Clément Léger
2024-05-17 14:52 ` Clément Léger
2024-05-17 14:52 ` Clément Léger
2024-05-17 16:44 ` Conor Dooley
2024-05-17 16:44 ` Conor Dooley
2024-05-17 16:44 ` Conor Dooley
2024-05-21 7:58 ` Clément Léger
2024-05-21 7:58 ` Clément Léger
2024-05-21 7:58 ` Clément Léger
2024-05-17 14:52 ` [PATCH v5 08/16] riscv: add ISA parsing for Zca, Zcf, Zcd and Zcb Clément Léger
2024-05-17 14:52 ` Clément Léger
2024-05-17 14:52 ` Clément Léger
2024-05-21 19:49 ` Conor Dooley
2024-05-21 19:49 ` Conor Dooley
2024-05-21 19:49 ` Conor Dooley
2024-05-22 7:20 ` Clément Léger
2024-05-22 7:20 ` Clément Léger
2024-05-22 7:20 ` Clément Léger
2024-05-30 21:13 ` Palmer Dabbelt
2024-05-30 21:13 ` Palmer Dabbelt
2024-05-30 21:13 ` Palmer Dabbelt
2024-06-04 7:18 ` Clément Léger
2024-06-04 7:18 ` Clément Léger
2024-06-04 7:18 ` Clément Léger
2024-05-17 14:52 ` [PATCH v5 09/16] riscv: hwprobe: export Zca, Zcf, Zcd and Zcb ISA extensions Clément Léger
2024-05-17 14:52 ` Clément Léger
2024-05-17 14:52 ` Clément Léger
2024-05-30 15:25 ` Charlie Jenkins
2024-05-30 15:25 ` Charlie Jenkins
2024-05-30 15:25 ` Charlie Jenkins
2024-05-17 14:52 ` [PATCH v5 10/16] RISC-V: KVM: Allow Zca, Zcf, Zcd and Zcb extensions for Guest/VM Clément Léger
2024-05-17 14:52 ` Clément Léger
2024-05-17 14:52 ` Clément Léger
2024-05-17 14:52 ` [PATCH v5 11/16] KVM: riscv: selftests: Add some Zc* extensions to get-reg-list test Clément Léger
2024-05-17 14:52 ` Clément Léger
2024-05-17 14:52 ` Clément Léger
2024-05-17 14:52 ` [PATCH v5 12/16] dt-bindings: riscv: add Zcmop ISA extension description Clément Léger
2024-05-17 14:52 ` Clément Léger
2024-05-17 14:52 ` Clément Léger
2024-05-17 14:52 ` [PATCH v5 13/16] riscv: add ISA extension parsing for Zcmop Clément Léger
2024-05-17 14:52 ` Clément Léger
2024-05-17 14:52 ` Clément Léger
2024-05-30 15:48 ` Charlie Jenkins
2024-05-30 15:48 ` Charlie Jenkins
2024-05-30 15:48 ` Charlie Jenkins
2024-05-17 14:52 ` [PATCH v5 14/16] riscv: hwprobe: export Zcmop ISA extension Clément Léger
2024-05-17 14:52 ` Clément Léger
2024-05-17 14:52 ` Clément Léger
2024-05-17 14:52 ` [PATCH v5 15/16] RISC-V: KVM: Allow Zcmop extension for Guest/VM Clément Léger
2024-05-17 14:52 ` Clément Léger
2024-05-17 14:52 ` Clément Léger
2024-05-17 14:52 ` [PATCH v5 16/16] KVM: riscv: selftests: Add Zcmop extension to get-reg-list test Clément Léger
2024-05-17 14:52 ` Clément Léger
2024-05-17 14:52 ` Clément Léger
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