From: Nicolin Chen <nicolinc@nvidia.com>
To: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Cc: <iommu@lists.linux.dev>, <linux-arm-kernel@lists.infradead.org>,
<robin.murphy@arm.com>, <will@kernel.org>, <joro@8bytes.org>,
<jgg@nvidia.com>, <ryan.roberts@arm.com>, <kevin.tian@intel.com>,
<mshavit@google.com>, <eric.auger@redhat.com>,
<joao.m.martins@oracle.com>, <jiangkunkun@huawei.com>,
<zhukeqian1@huawei.com>, <linuxarm@huawei.com>
Subject: Re: [PATCH v5 6/6] iommu/arm-smmu-v3: Enable HTTU for stage1 with io-pgtable mapping
Date: Thu, 6 Jun 2024 16:47:57 -0700 [thread overview]
Message-ID: <ZmJKrcPeVdcf3xyR@Asurada-Nvidia> (raw)
In-Reply-To: <20240606133302.17540-7-shameerali.kolothum.thodi@huawei.com>
On Thu, Jun 06, 2024 at 02:33:02PM +0100, Shameer Kolothum wrote:
> From: Kunkun Jiang <jiangkunkun@huawei.com>
>
> If io-pgtable quirk flag indicates support for hardware update of
> dirty state, enable HA/HD bits in the SMMU CD and also set the DBM
> bit in the page descriptor.
>
> Now report the dirty page tracking capability of SMMUv3 and
> select IOMMUFD_DRIVER for ARM_SMMU_V3 if IOMMUFD is enabled.
>
> Co-developed-by: Keqian Zhu <zhukeqian1@huawei.com>
> Signed-off-by: Keqian Zhu <zhukeqian1@huawei.com>
> Signed-off-by: Kunkun Jiang <jiangkunkun@huawei.com>
> Signed-off-by: Joao Martins <joao.m.martins@oracle.com>
> Reviewed-by: Ryan Roberts <ryan.roberts@arm.com>
> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
With a nit:
> +static bool arm_smmu_dbm_capable(struct arm_smmu_device *smmu)
> +{
> + u32 features = (ARM_SMMU_FEAT_HD | ARM_SMMU_FEAT_COHERENCY);
> +
> + return (smmu->features & features) == features;
Following the existing coding style in the driver:
return (smmu->features & ARM_SMMU_FEAT_HD) &&
(smmu->features & ARM_SMMU_FEAT_COHERENCY);
And inline?
Thanks
Nicolin
WARNING: multiple messages have this Message-ID (diff)
From: Nicolin Chen <nicolinc@nvidia.com>
To: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Cc: <iommu@lists.linux.dev>, <linux-arm-kernel@lists.infradead.org>,
<robin.murphy@arm.com>, <will@kernel.org>, <joro@8bytes.org>,
<jgg@nvidia.com>, <ryan.roberts@arm.com>, <kevin.tian@intel.com>,
<mshavit@google.com>, <eric.auger@redhat.com>,
<joao.m.martins@oracle.com>, <jiangkunkun@huawei.com>,
<zhukeqian1@huawei.com>, <linuxarm@huawei.com>
Subject: Re: [PATCH v5 6/6] iommu/arm-smmu-v3: Enable HTTU for stage1 with io-pgtable mapping
Date: Thu, 6 Jun 2024 16:47:57 -0700 [thread overview]
Message-ID: <ZmJKrcPeVdcf3xyR@Asurada-Nvidia> (raw)
In-Reply-To: <20240606133302.17540-7-shameerali.kolothum.thodi@huawei.com>
On Thu, Jun 06, 2024 at 02:33:02PM +0100, Shameer Kolothum wrote:
> From: Kunkun Jiang <jiangkunkun@huawei.com>
>
> If io-pgtable quirk flag indicates support for hardware update of
> dirty state, enable HA/HD bits in the SMMU CD and also set the DBM
> bit in the page descriptor.
>
> Now report the dirty page tracking capability of SMMUv3 and
> select IOMMUFD_DRIVER for ARM_SMMU_V3 if IOMMUFD is enabled.
>
> Co-developed-by: Keqian Zhu <zhukeqian1@huawei.com>
> Signed-off-by: Keqian Zhu <zhukeqian1@huawei.com>
> Signed-off-by: Kunkun Jiang <jiangkunkun@huawei.com>
> Signed-off-by: Joao Martins <joao.m.martins@oracle.com>
> Reviewed-by: Ryan Roberts <ryan.roberts@arm.com>
> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
With a nit:
> +static bool arm_smmu_dbm_capable(struct arm_smmu_device *smmu)
> +{
> + u32 features = (ARM_SMMU_FEAT_HD | ARM_SMMU_FEAT_COHERENCY);
> +
> + return (smmu->features & features) == features;
Following the existing coding style in the driver:
return (smmu->features & ARM_SMMU_FEAT_HD) &&
(smmu->features & ARM_SMMU_FEAT_COHERENCY);
And inline?
Thanks
Nicolin
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next prev parent reply other threads:[~2024-06-06 23:48 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-06 13:32 [PATCH v5 0/6] Add IOMMUFD dirty tracking support for SMMUv3 Shameer Kolothum
2024-06-06 13:32 ` Shameer Kolothum
2024-06-06 13:32 ` [PATCH v5 1/6] iommu/arm-smmu-v3: Factor out a common domain alloc Shameer Kolothum
2024-06-06 13:32 ` Shameer Kolothum
2024-06-06 18:08 ` Jason Gunthorpe
2024-06-06 18:08 ` Jason Gunthorpe
2024-06-06 22:12 ` Nicolin Chen
2024-06-06 22:12 ` Nicolin Chen
2024-06-06 13:32 ` [PATCH v5 2/6] iommu/arm-smmu-v3: Add support for domain_alloc_user fn Shameer Kolothum
2024-06-06 13:32 ` Shameer Kolothum
2024-06-06 22:13 ` Nicolin Chen
2024-06-06 22:13 ` Nicolin Chen
2024-06-06 13:32 ` [PATCH v5 3/6] iommu/arm-smmu-v3: Add feature detection for HTTU Shameer Kolothum
2024-06-06 13:32 ` Shameer Kolothum
2024-06-06 23:10 ` Nicolin Chen
2024-06-06 23:10 ` Nicolin Chen
2024-06-07 8:04 ` Shameerali Kolothum Thodi
2024-06-07 8:04 ` Shameerali Kolothum Thodi
2024-06-07 21:21 ` Nicolin Chen
2024-06-07 21:21 ` Nicolin Chen
2024-06-06 13:33 ` [PATCH v5 4/6] iommu/io-pgtable-arm: Add read_and_clear_dirty() support Shameer Kolothum
2024-06-06 13:33 ` Shameer Kolothum
2024-06-06 13:33 ` [PATCH v5 5/6] iommu/arm-smmu-v3: Add support for dirty tracking in domain alloc Shameer Kolothum
2024-06-06 13:33 ` Shameer Kolothum
2024-06-06 23:39 ` Nicolin Chen
2024-06-06 23:39 ` Nicolin Chen
2024-06-06 13:33 ` [PATCH v5 6/6] iommu/arm-smmu-v3: Enable HTTU for stage1 with io-pgtable mapping Shameer Kolothum
2024-06-06 13:33 ` Shameer Kolothum
2024-06-06 23:47 ` Nicolin Chen [this message]
2024-06-06 23:47 ` Nicolin Chen
2024-06-07 9:49 ` [PATCH v5 0/6] Add IOMMUFD dirty tracking support for SMMUv3 Tian, Kevin
2024-06-07 9:49 ` Tian, Kevin
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