From: Deepak Gupta <debug@rivosinc.com>
To: Jisheng Zhang <jszhang@kernel.org>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Samuel Holland <samuel.holland@sifive.com>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 0/6] riscv: convert bottom half of exception handling to C
Date: Wed, 19 Jun 2024 09:30:10 -0700 [thread overview]
Message-ID: <ZnMHku8LSGmuHZQS@debug.ba.rivosinc.com> (raw)
In-Reply-To: <20240616170553.2832-1-jszhang@kernel.org>
On Mon, Jun 17, 2024 at 01:05:47AM +0800, Jisheng Zhang wrote:
>For readability, maintainability and future scalability, convert the
>bottom half of the exception handling to C.
>
>During the conversion, I found Anton fixed a performance issue
>and my patches will touch the same exception asm code, so I include
>Anton's patch for completeness. I also cooked a similar patch to avoid
>corrupting the RAS in ret_from_fork() per the inspiration.
nit: Probably corruption is wrong word here giving the notion that software
got some capability to corrupt uarch structures. It's simply mismatched # of
call and # of rets. Imbalance (instead of calling it corruption) in return
address stack (RAS) leading to incorret predictions on return.
>
>Mostly the assembly code is converted to C in a relatively
>straightforward manner.
>
>However, there are two modifications I need to mention:
>
>1. the CSR_CAUSE reg reading and saving is moved to the C code
>because we need the cause to dispatch the exception handling,
>if we keep the cause reading and saving, we either pass it to
>do_traps() via. 2nd param or get it from pt_regs which an extra
>memory load is needed, I don't like any of the two solutions becase
>the exception handling sits in hot code path, every instruction
>matters.
>
>2.To cope with SIFIVE_CIP_453 errata, it looks like we don't need
>alternative mechanism any more after the asm->c convertion. Just
>replace the excp_vect_table two entries.
>
>
>
>Anton Blanchard (1):
> riscv: Improve exception and system call latency
>
>Jisheng Zhang (5):
> riscv: avoid corrupting the RAS
> riscv: convert bottom half of exception handling to C
> riscv: errata: remove ALT_INSN_FAULT and ALT_PAGE_FAULT
> riscv: errata: sifive: remove NOMMU handling
> riscv: remove asmlinkage from updated functions
>
> arch/riscv/errata/sifive/errata.c | 25 +++++++---
> arch/riscv/errata/sifive/errata_cip_453.S | 4 --
> arch/riscv/include/asm/asm-prototypes.h | 7 +--
> arch/riscv/include/asm/errata_list.h | 21 ++------
> arch/riscv/kernel/entry.S | 61 ++---------------------
> arch/riscv/kernel/stacktrace.c | 4 +-
> arch/riscv/kernel/traps.c | 57 ++++++++++++++++++---
> 7 files changed, 81 insertions(+), 98 deletions(-)
>
>--
>2.43.0
>
>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Deepak Gupta <debug@rivosinc.com>
To: Jisheng Zhang <jszhang@kernel.org>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Samuel Holland <samuel.holland@sifive.com>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 0/6] riscv: convert bottom half of exception handling to C
Date: Wed, 19 Jun 2024 09:30:10 -0700 [thread overview]
Message-ID: <ZnMHku8LSGmuHZQS@debug.ba.rivosinc.com> (raw)
In-Reply-To: <20240616170553.2832-1-jszhang@kernel.org>
On Mon, Jun 17, 2024 at 01:05:47AM +0800, Jisheng Zhang wrote:
>For readability, maintainability and future scalability, convert the
>bottom half of the exception handling to C.
>
>During the conversion, I found Anton fixed a performance issue
>and my patches will touch the same exception asm code, so I include
>Anton's patch for completeness. I also cooked a similar patch to avoid
>corrupting the RAS in ret_from_fork() per the inspiration.
nit: Probably corruption is wrong word here giving the notion that software
got some capability to corrupt uarch structures. It's simply mismatched # of
call and # of rets. Imbalance (instead of calling it corruption) in return
address stack (RAS) leading to incorret predictions on return.
>
>Mostly the assembly code is converted to C in a relatively
>straightforward manner.
>
>However, there are two modifications I need to mention:
>
>1. the CSR_CAUSE reg reading and saving is moved to the C code
>because we need the cause to dispatch the exception handling,
>if we keep the cause reading and saving, we either pass it to
>do_traps() via. 2nd param or get it from pt_regs which an extra
>memory load is needed, I don't like any of the two solutions becase
>the exception handling sits in hot code path, every instruction
>matters.
>
>2.To cope with SIFIVE_CIP_453 errata, it looks like we don't need
>alternative mechanism any more after the asm->c convertion. Just
>replace the excp_vect_table two entries.
>
>
>
>Anton Blanchard (1):
> riscv: Improve exception and system call latency
>
>Jisheng Zhang (5):
> riscv: avoid corrupting the RAS
> riscv: convert bottom half of exception handling to C
> riscv: errata: remove ALT_INSN_FAULT and ALT_PAGE_FAULT
> riscv: errata: sifive: remove NOMMU handling
> riscv: remove asmlinkage from updated functions
>
> arch/riscv/errata/sifive/errata.c | 25 +++++++---
> arch/riscv/errata/sifive/errata_cip_453.S | 4 --
> arch/riscv/include/asm/asm-prototypes.h | 7 +--
> arch/riscv/include/asm/errata_list.h | 21 ++------
> arch/riscv/kernel/entry.S | 61 ++---------------------
> arch/riscv/kernel/stacktrace.c | 4 +-
> arch/riscv/kernel/traps.c | 57 ++++++++++++++++++---
> 7 files changed, 81 insertions(+), 98 deletions(-)
>
>--
>2.43.0
>
>
next prev parent reply other threads:[~2024-06-19 16:30 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-16 17:05 [PATCH 0/6] riscv: convert bottom half of exception handling to C Jisheng Zhang
2024-06-16 17:05 ` Jisheng Zhang
2024-06-16 17:05 ` [PATCH 1/6] riscv: Improve exception and system call latency Jisheng Zhang
2024-06-16 17:05 ` Jisheng Zhang
2024-06-22 0:15 ` Charlie Jenkins
2024-06-22 0:15 ` Charlie Jenkins
2024-06-22 0:50 ` Jisheng Zhang
2024-06-22 0:50 ` Jisheng Zhang
2024-06-16 17:05 ` [PATCH 2/6] riscv: avoid corrupting the RAS Jisheng Zhang
2024-06-16 17:05 ` Jisheng Zhang
2024-06-19 23:02 ` Cyril Bur
2024-06-19 23:02 ` Cyril Bur
2024-06-16 17:05 ` [PATCH 3/6] riscv: convert bottom half of exception handling to C Jisheng Zhang
2024-06-16 17:05 ` Jisheng Zhang
2024-06-19 17:04 ` Deepak Gupta
2024-06-19 17:04 ` Deepak Gupta
2024-06-20 0:02 ` Cyril Bur
2024-06-20 0:02 ` Cyril Bur
2024-06-20 8:06 ` Clément Léger
2024-06-20 8:06 ` Clément Léger
2024-06-20 23:56 ` Jisheng Zhang
2024-06-20 23:56 ` Jisheng Zhang
2024-06-21 19:02 ` Deepak Gupta
2024-06-21 19:02 ` Deepak Gupta
2024-06-20 23:10 ` Cyril Bur
2024-06-20 23:10 ` Cyril Bur
2024-06-20 23:49 ` Jisheng Zhang
2024-06-20 23:49 ` Jisheng Zhang
2024-06-24 18:49 ` [PATCH 3/6] " Charlie Jenkins
2024-06-24 18:49 ` Charlie Jenkins
2024-06-24 23:10 ` Cyril Bur
2024-06-24 23:10 ` Cyril Bur
2024-06-16 17:05 ` [PATCH 4/6] riscv: errata: remove ALT_INSN_FAULT and ALT_PAGE_FAULT Jisheng Zhang
2024-06-16 17:05 ` Jisheng Zhang
2024-06-16 17:05 ` [PATCH 5/6] riscv: errata: sifive: remove NOMMU handling Jisheng Zhang
2024-06-16 17:05 ` Jisheng Zhang
2024-06-16 17:05 ` [PATCH 6/6] riscv: remove asmlinkage from updated functions Jisheng Zhang
2024-06-16 17:05 ` Jisheng Zhang
2024-06-24 18:53 ` Charlie Jenkins
2024-06-24 18:53 ` Charlie Jenkins
2024-06-18 22:16 ` [PATCH 0/6] riscv: convert bottom half of exception handling to C Cyril Bur
2024-06-18 22:16 ` Cyril Bur
2024-06-19 15:11 ` Jisheng Zhang
2024-06-19 15:11 ` Jisheng Zhang
2024-06-19 23:59 ` [CAUTION - External Sender] " Cyril Bur
2024-06-19 23:59 ` Cyril Bur
2024-06-19 16:30 ` Deepak Gupta [this message]
2024-06-19 16:30 ` Deepak Gupta
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=ZnMHku8LSGmuHZQS@debug.ba.rivosinc.com \
--to=debug@rivosinc.com \
--cc=aou@eecs.berkeley.edu \
--cc=jszhang@kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=samuel.holland@sifive.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.