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From: William McVicker <willmcvicker@google.com>
To: "André Draszik" <andre.draszik@linaro.org>
Cc: Vinod Koul <vkoul@kernel.org>,
	Kishon Vijay Abraham I <kishon@kernel.org>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Peter Griffin <peter.griffin@linaro.org>,
	Marek Szyprowski <m.szyprowski@samsung.com>,
	Sylwester Nawrocki <s.nawrocki@samsung.com>,
	Alim Akhtar <alim.akhtar@samsung.com>,
	Sam Protsenko <semen.protsenko@linaro.org>,
	Krzysztof Kozlowski <krzk@kernel.org>,
	Tudor Ambarus <tudor.ambarus@linaro.org>,
	Roy Luo <royluo@google.com>,
	kernel-team@android.com, linux-phy@lists.infradead.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-samsung-soc@vger.kernel.org
Subject: Re: [PATCH v3 4/6] phy: exynos5-usbdrd: convert (phy) register access clock to clk_bulk
Date: Fri, 21 Jun 2024 17:03:45 -0700	[thread overview]
Message-ID: <ZnYU4TRR3gUbadWR@google.com> (raw)
In-Reply-To: <20240617-usb-phy-gs101-v3-4-b66de9ae7424@linaro.org>

On 06/17/2024, André Draszik wrote:
> In preparation for support for additional platforms, convert the phy
> register access clock to using the clk_bulk interfaces.
> 
> Newer SoCs like Google Tensor gs101 require additional clocks for
> access to additional (different) register areas (PHY, PMA, PCS), and
> converting to clk_bulk simplifies addition of those extra clocks.
> 
> Signed-off-by: André Draszik <andre.draszik@linaro.org>

Tested-by: Will McVicker <willmcvicker@google.com>

[...]

Thanks,
Will

-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

WARNING: multiple messages have this Message-ID (diff)
From: William McVicker <willmcvicker@google.com>
To: "André Draszik" <andre.draszik@linaro.org>
Cc: Vinod Koul <vkoul@kernel.org>,
	Kishon Vijay Abraham I <kishon@kernel.org>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Peter Griffin <peter.griffin@linaro.org>,
	Marek Szyprowski <m.szyprowski@samsung.com>,
	Sylwester Nawrocki <s.nawrocki@samsung.com>,
	Alim Akhtar <alim.akhtar@samsung.com>,
	Sam Protsenko <semen.protsenko@linaro.org>,
	Krzysztof Kozlowski <krzk@kernel.org>,
	Tudor Ambarus <tudor.ambarus@linaro.org>,
	Roy Luo <royluo@google.com>,
	kernel-team@android.com, linux-phy@lists.infradead.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-samsung-soc@vger.kernel.org
Subject: Re: [PATCH v3 4/6] phy: exynos5-usbdrd: convert (phy) register access clock to clk_bulk
Date: Fri, 21 Jun 2024 17:03:45 -0700	[thread overview]
Message-ID: <ZnYU4TRR3gUbadWR@google.com> (raw)
In-Reply-To: <20240617-usb-phy-gs101-v3-4-b66de9ae7424@linaro.org>

On 06/17/2024, André Draszik wrote:
> In preparation for support for additional platforms, convert the phy
> register access clock to using the clk_bulk interfaces.
> 
> Newer SoCs like Google Tensor gs101 require additional clocks for
> access to additional (different) register areas (PHY, PMA, PCS), and
> converting to clk_bulk simplifies addition of those extra clocks.
> 
> Signed-off-by: André Draszik <andre.draszik@linaro.org>

Tested-by: Will McVicker <willmcvicker@google.com>

[...]

Thanks,
Will

  reply	other threads:[~2024-06-22  0:03 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-06-17 16:44 [PATCH v3 0/6] USB31DRD phy support for Google Tensor gs101 (HS & SS) André Draszik
2024-06-17 16:44 ` André Draszik
2024-06-17 16:44 ` [PATCH v3 1/6] dt-bindings: phy: samsung,usb3-drd-phy: add gs101 compatible André Draszik
2024-06-17 16:44   ` André Draszik
2024-06-24  5:19   ` Krzysztof Kozlowski
2024-06-24  5:19     ` Krzysztof Kozlowski
2024-06-24 11:13   ` Peter Griffin
2024-06-24 11:13     ` Peter Griffin
2024-06-17 16:44 ` [PATCH v3 2/6] phy: exynos5-usbdrd: support isolating HS and SS ports independently André Draszik
2024-06-17 16:44   ` André Draszik
2024-06-22  0:02   ` William McVicker
2024-06-22  0:02     ` William McVicker
2024-06-24 11:20   ` Peter Griffin
2024-06-24 11:20     ` Peter Griffin
2024-06-17 16:44 ` [PATCH v3 3/6] phy: exynos5-usbdrd: convert core clocks to clk_bulk André Draszik
2024-06-17 16:44   ` André Draszik
2024-06-22  0:05   ` William McVicker
2024-06-22  0:05     ` William McVicker
2024-06-24 11:22   ` Peter Griffin
2024-06-24 11:22     ` Peter Griffin
2024-06-17 16:44 ` [PATCH v3 4/6] phy: exynos5-usbdrd: convert (phy) register access clock " André Draszik
2024-06-17 16:44   ` André Draszik
2024-06-22  0:03   ` William McVicker [this message]
2024-06-22  0:03     ` William McVicker
2024-06-24 11:23   ` Peter Griffin
2024-06-24 11:23     ` Peter Griffin
2024-06-17 16:44 ` [PATCH v3 5/6] phy: exynos5-usbdrd: convert Vbus supplies to regulator_bulk André Draszik
2024-06-17 16:44   ` André Draszik
2024-06-22  0:06   ` William McVicker
2024-06-22  0:06     ` William McVicker
2024-06-24 11:28   ` Peter Griffin
2024-06-24 11:28     ` Peter Griffin
2024-06-17 16:44 ` [PATCH v3 6/6] phy: exynos5-usbdrd: support Exynos USBDRD 3.1 combo phy (HS & SS) André Draszik
2024-06-17 16:44   ` André Draszik
2024-06-22  0:07   ` William McVicker
2024-06-22  0:07     ` William McVicker
2024-06-24 11:33   ` Peter Griffin
2024-06-24 11:33     ` Peter Griffin
2024-06-22  0:24 ` [PATCH v3 0/6] USB31DRD phy support for Google Tensor gs101 " William McVicker
2024-06-22  0:24   ` William McVicker
2024-07-02 13:36 ` Vinod Koul
2024-07-02 13:36   ` Vinod Koul

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