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From: Charlie Jenkins <charlie@rivosinc.com>
To: Samuel Holland <samuel.holland@sifive.com>
Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev,
	linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org,
	Heiko Stuebner <heiko@sntech.de>, Conor Dooley <conor@kernel.org>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Jisheng Zhang <jszhang@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
	Jernej Skrabec <jernej.skrabec@gmail.com>,
	Samuel Holland <samuel@sholland.org>,
	Jonathan Corbet <corbet@lwn.net>, Shuah Khan <shuah@kernel.org>,
	Guo Ren <guoren@kernel.org>, Evan Green <evan@rivosinc.com>,
	Andy Chiu <andy.chiu@sifive.com>,
	Jessica Clarke <jrtc27@jrtc27.com>
Subject: Re: [PATCH v3 07/13] riscv: csr: Add CSR encodings for VCSR_VXRM/VCSR_VXSAT
Date: Mon, 1 Jul 2024 22:46:08 -0700	[thread overview]
Message-ID: <ZoOUIJIxnwpqxBHR@ghost> (raw)
In-Reply-To: <54232f3e-4fea-4996-a90b-6de51e1c51e0@sifive.com>

On Mon, Jul 01, 2024 at 10:49:23AM -0500, Samuel Holland wrote:
> Hi Charlie,
> 
> On 2024-06-19 6:57 PM, Charlie Jenkins wrote:
> > The VXRM vector csr for xtheadvector has an encoding of 0xa and VXSAT
> > has an encoding of 0x9.
> > 
> > Co-developed-by: Heiko Stuebner <heiko@sntech.de>
> > Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> > Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
> > ---
> >  arch/riscv/include/asm/csr.h | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
> > index 18e178d83401..9086639a3dde 100644
> > --- a/arch/riscv/include/asm/csr.h
> > +++ b/arch/riscv/include/asm/csr.h
> > @@ -220,6 +220,8 @@
> >  #define VCSR_VXRM_MASK			3
> >  #define VCSR_VXRM_SHIFT			1
> >  #define VCSR_VXSAT_MASK			1
> > +#define VCSR_VXSAT			0x9
> > +#define VCSR_VXRM			0xa
> 
> These are normal CSR indexes, so the prefix should be just "CSR_".

Ok, I can change them.

- Charlie

> 
> Regards,
> Samuel
> 
> >  
> >  /* symbolic CSR names: */
> >  #define CSR_CYCLE		0xc00
> > 
> 

WARNING: multiple messages have this Message-ID (diff)
From: Charlie Jenkins <charlie@rivosinc.com>
To: Samuel Holland <samuel.holland@sifive.com>
Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev,
	linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org,
	Heiko Stuebner <heiko@sntech.de>, Conor Dooley <conor@kernel.org>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Jisheng Zhang <jszhang@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
	Jernej Skrabec <jernej.skrabec@gmail.com>,
	Samuel Holland <samuel@sholland.org>,
	Jonathan Corbet <corbet@lwn.net>, Shuah Khan <shuah@kernel.org>,
	Guo Ren <guoren@kernel.org>, Evan Green <evan@rivosinc.com>,
	Andy Chiu <andy.chiu@sifive.com>,
	Jessica Clarke <jrtc27@jrtc27.com>
Subject: Re: [PATCH v3 07/13] riscv: csr: Add CSR encodings for VCSR_VXRM/VCSR_VXSAT
Date: Mon, 1 Jul 2024 22:46:08 -0700	[thread overview]
Message-ID: <ZoOUIJIxnwpqxBHR@ghost> (raw)
In-Reply-To: <54232f3e-4fea-4996-a90b-6de51e1c51e0@sifive.com>

On Mon, Jul 01, 2024 at 10:49:23AM -0500, Samuel Holland wrote:
> Hi Charlie,
> 
> On 2024-06-19 6:57 PM, Charlie Jenkins wrote:
> > The VXRM vector csr for xtheadvector has an encoding of 0xa and VXSAT
> > has an encoding of 0x9.
> > 
> > Co-developed-by: Heiko Stuebner <heiko@sntech.de>
> > Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> > Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
> > ---
> >  arch/riscv/include/asm/csr.h | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
> > index 18e178d83401..9086639a3dde 100644
> > --- a/arch/riscv/include/asm/csr.h
> > +++ b/arch/riscv/include/asm/csr.h
> > @@ -220,6 +220,8 @@
> >  #define VCSR_VXRM_MASK			3
> >  #define VCSR_VXRM_SHIFT			1
> >  #define VCSR_VXSAT_MASK			1
> > +#define VCSR_VXSAT			0x9
> > +#define VCSR_VXRM			0xa
> 
> These are normal CSR indexes, so the prefix should be just "CSR_".

Ok, I can change them.

- Charlie

> 
> Regards,
> Samuel
> 
> >  
> >  /* symbolic CSR names: */
> >  #define CSR_CYCLE		0xc00
> > 
> 

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  reply	other threads:[~2024-07-02  5:46 UTC|newest]

Thread overview: 54+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-06-19 23:57 [PATCH v3 00/13] riscv: Add support for xtheadvector Charlie Jenkins
2024-06-19 23:57 ` Charlie Jenkins
2024-06-19 23:57 ` [PATCH v3 01/13] dt-bindings: riscv: Add xtheadvector ISA extension description Charlie Jenkins
2024-06-19 23:57   ` Charlie Jenkins
2024-06-19 23:57 ` [PATCH v3 02/13] dt-bindings: cpus: add a thead vlen register length property Charlie Jenkins
2024-06-19 23:57   ` Charlie Jenkins
2024-06-19 23:57 ` [PATCH v3 03/13] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree Charlie Jenkins
2024-06-19 23:57   ` Charlie Jenkins
2024-06-20 10:06   ` Chen-Yu Tsai
2024-06-20 10:06     ` Chen-Yu Tsai
2024-07-01 15:27   ` Samuel Holland
2024-07-01 15:27     ` Samuel Holland
2024-07-01 16:07     ` Conor Dooley
2024-07-01 16:07       ` Conor Dooley
2024-07-01 16:11       ` Samuel Holland
2024-07-01 16:11         ` Samuel Holland
2024-07-01 16:31         ` Conor Dooley
2024-07-01 16:31           ` Conor Dooley
2024-07-02  9:46           ` Yu-Chien Peter Lin
2024-07-02  9:46             ` Yu-Chien Peter Lin
2024-07-02 15:39             ` Conor Dooley
2024-07-02 15:39               ` Conor Dooley
2024-06-19 23:57 ` [PATCH v3 04/13] riscv: Add thead and xtheadvector as a vendor extension Charlie Jenkins
2024-06-19 23:57   ` Charlie Jenkins
2024-06-19 23:57 ` [PATCH v3 05/13] riscv: vector: Use vlenb from DT for thead Charlie Jenkins
2024-06-19 23:57   ` Charlie Jenkins
2024-07-01 14:06   ` Conor Dooley
2024-07-01 14:06     ` Conor Dooley
2024-07-10  7:11   ` Guo Ren
2024-07-10  7:11     ` Guo Ren
2024-06-19 23:57 ` [PATCH v3 06/13] RISC-V: define the elements of the VCSR vector CSR Charlie Jenkins
2024-06-19 23:57   ` Charlie Jenkins
2024-06-19 23:57 ` [PATCH v3 07/13] riscv: csr: Add CSR encodings for VCSR_VXRM/VCSR_VXSAT Charlie Jenkins
2024-06-19 23:57   ` Charlie Jenkins
2024-07-01 15:49   ` Samuel Holland
2024-07-01 15:49     ` Samuel Holland
2024-07-02  5:46     ` Charlie Jenkins [this message]
2024-07-02  5:46       ` Charlie Jenkins
2024-06-19 23:57 ` [PATCH v3 08/13] riscv: Add xtheadvector instruction definitions Charlie Jenkins
2024-06-19 23:57   ` Charlie Jenkins
2024-06-19 23:57 ` [PATCH v3 09/13] riscv: vector: Support xtheadvector save/restore Charlie Jenkins
2024-06-19 23:57   ` Charlie Jenkins
2024-07-01 16:20   ` Samuel Holland
2024-07-01 16:20     ` Samuel Holland
2024-07-02  5:51     ` Charlie Jenkins
2024-07-02  5:51       ` Charlie Jenkins
2024-06-19 23:57 ` [PATCH v3 10/13] riscv: hwprobe: Add thead vendor extension probing Charlie Jenkins
2024-06-19 23:57   ` Charlie Jenkins
2024-06-19 23:57 ` [PATCH v3 11/13] riscv: hwprobe: Document thead vendor extensions and xtheadvector extension Charlie Jenkins
2024-06-19 23:57   ` Charlie Jenkins
2024-06-19 23:57 ` [PATCH v3 12/13] selftests: riscv: Fix vector tests Charlie Jenkins
2024-06-19 23:57   ` Charlie Jenkins
2024-06-19 23:57 ` [PATCH v3 13/13] selftests: riscv: Support xtheadvector in " Charlie Jenkins
2024-06-19 23:57   ` Charlie Jenkins

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