From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: "Manna, Animesh" <animesh.manna@intel.com>
Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 10/14] drm/i915/dsb: Introduce intel_dsb_chain()
Date: Wed, 3 Jul 2024 15:20:19 +0300 [thread overview]
Message-ID: <ZoVCAxHLvC_D9N1M@intel.com> (raw)
In-Reply-To: <PH7PR11MB59816D24912D1E83CC8B4CF6F9DD2@PH7PR11MB5981.namprd11.prod.outlook.com>
On Wed, Jul 03, 2024 at 12:10:38PM +0000, Manna, Animesh wrote:
>
>
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> > Syrjala
> > Sent: Tuesday, June 25, 2024 12:40 AM
> > To: intel-gfx@lists.freedesktop.org
> > Subject: [PATCH 10/14] drm/i915/dsb: Introduce intel_dsb_chain()
> >
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > In order to handle the DEwake tricks without involving the CPU we need a
> > mechanism by which one DSB can start another one. Add a basic function to
> > do so. We'll extend it later with additional code to actually deal with DEwake.
>
> Is chained DSB concept restricting to only 2 DSB instance or can be extended to available/max DSB instances?
>
> Are we exposing full chain of DSB to user or can be restrict to primary DSB which will control other instances?
You can start any DSB from any other DSB.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_dsb.c | 42 ++++++++++++++++++++++++
> > drivers/gpu/drm/i915/display/intel_dsb.h | 3 ++
> > 2 files changed, 45 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
> > b/drivers/gpu/drm/i915/display/intel_dsb.c
> > index 092cf082ac39..4c0519c41f16 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> > @@ -502,6 +502,48 @@ static u32 dsb_error_int_en(struct intel_display
> > *display)
> > return errors;
> > }
> >
> > +static void _intel_dsb_chain(struct intel_atomic_state *state,
> > + struct intel_dsb *dsb,
> > + struct intel_dsb *chained_dsb,
> > + u32 ctrl)
>
> I do not see any usage of ctrl variable in this patch, maybe good to add wherever will be using it.
It's in the next patch.
>
> Regards,
> Animesh
> > +{
> > + struct intel_display *display = to_intel_display(state->base.dev);
> > + struct intel_crtc *crtc = dsb->crtc;
> > + enum pipe pipe = crtc->pipe;
> > + u32 tail;
> > +
> > + if (drm_WARN_ON(display->drm, dsb->id == chained_dsb->id))
> > + return;
> > +
> > + tail = chained_dsb->free_pos * 4;
> > + if (drm_WARN_ON(display->drm, !IS_ALIGNED(tail,
> > CACHELINE_BYTES)))
> > + return;
> > +
> > + intel_dsb_reg_write(dsb, DSB_CTRL(pipe, chained_dsb->id),
> > + ctrl | DSB_ENABLE);
> > +
> > + intel_dsb_reg_write(dsb, DSB_CHICKEN(pipe, chained_dsb->id),
> > + dsb_chicken(state, crtc));
> > +
> > + intel_dsb_reg_write(dsb, DSB_INTERRUPT(pipe, chained_dsb->id),
> > + dsb_error_int_status(display) |
> > DSB_PROG_INT_STATUS |
> > + dsb_error_int_en(display));
> > +
> > + intel_dsb_reg_write(dsb, DSB_HEAD(pipe, chained_dsb->id),
> > + intel_dsb_buffer_ggtt_offset(&chained_dsb-
> > >dsb_buf));
> > +
> > + intel_dsb_reg_write(dsb, DSB_TAIL(pipe, chained_dsb->id),
> > + intel_dsb_buffer_ggtt_offset(&chained_dsb-
> > >dsb_buf) + tail); }
> > +
> > +void intel_dsb_chain(struct intel_atomic_state *state,
> > + struct intel_dsb *dsb,
> > + struct intel_dsb *chained_dsb)
> > +{
> > + _intel_dsb_chain(state, dsb, chained_dsb,
> > + 0);
> > +}
> > +
> > static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl,
> > int hw_dewake_scanline)
> > {
> > diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
> > b/drivers/gpu/drm/i915/display/intel_dsb.h
> > index d0737cefb393..e59fd7da0fc0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dsb.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dsb.h
> > @@ -45,6 +45,9 @@ void intel_dsb_wait_scanline_in(struct
> > intel_atomic_state *state, void intel_dsb_wait_scanline_out(struct
> > intel_atomic_state *state,
> > struct intel_dsb *dsb,
> > int lower, int upper);
> > +void intel_dsb_chain(struct intel_atomic_state *state,
> > + struct intel_dsb *dsb,
> > + struct intel_dsb *chained_dsb);
> >
> > void intel_dsb_commit(struct intel_dsb *dsb,
> > bool wait_for_vblank);
> > --
> > 2.44.2
>
--
Ville Syrjälä
Intel
next prev parent reply other threads:[~2024-07-03 12:20 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-24 19:10 [PATCH 00/14] drm/i915/dsb: Use chained DSBs for LUT programming Ville Syrjala
2024-06-24 19:10 ` [PATCH 01/14] drm/i915: Calculate vblank delay more accurately Ville Syrjala
2024-06-28 8:16 ` Manna, Animesh
2024-06-24 19:10 ` [PATCH 02/14] drm/i915: Make vrr_{enabling, disabling}() usable outside intel_display.c Ville Syrjala
2024-06-28 8:18 ` Manna, Animesh
2024-06-24 19:10 ` [PATCH 03/14] drm/i915/dsb: Hook up DSB error interrupts Ville Syrjala
2024-06-25 7:58 ` Jani Nikula
2024-06-25 13:58 ` [PATCH v2 " Ville Syrjala
2024-08-27 14:10 ` Manna, Animesh
2024-06-28 9:21 ` [PATCH " Manna, Animesh
2024-06-28 11:04 ` Ville Syrjälä
2024-06-24 19:10 ` [PATCH 04/14] drm/i915/dsb: Convert dewake_scanline to a hw scanline number earlier Ville Syrjala
2024-06-24 19:10 ` [PATCH 05/14] drm/i915/dsb: Shuffle code around Ville Syrjala
2024-07-03 5:49 ` Manna, Animesh
2024-06-24 19:10 ` [PATCH 06/14] drm/i915/dsb: Fix dewake scanline Ville Syrjala
2024-07-03 5:59 ` Manna, Animesh
2024-06-24 19:10 ` [PATCH 07/14] drm/i915/dsb: Account for VRR properly in DSB scanline stuff Ville Syrjala
2024-07-03 8:23 ` Manna, Animesh
2024-06-24 19:10 ` [PATCH 08/14] drm/i915/dsb: Precompute DSB_CHICKEN Ville Syrjala
2024-07-03 8:48 ` Manna, Animesh
2024-06-24 19:10 ` [PATCH 09/14] drm/i915/dsb: Introduce intel_dsb_wait_scanline_{in, out}() Ville Syrjala
2024-07-03 11:37 ` Manna, Animesh
2024-07-03 12:07 ` Ville Syrjälä
2024-07-03 12:10 ` Ville Syrjälä
2024-08-27 6:30 ` Manna, Animesh
2024-06-24 19:10 ` [PATCH 10/14] drm/i915/dsb: Introduce intel_dsb_chain() Ville Syrjala
2024-07-03 12:10 ` Manna, Animesh
2024-07-03 12:20 ` Ville Syrjälä [this message]
2024-08-21 15:05 ` Manna, Animesh
2024-08-23 12:45 ` Ville Syrjälä
2024-08-27 6:19 ` Manna, Animesh
2024-06-24 19:10 ` [PATCH 11/14] drm/i915/dsb: Allow intel_dsb_chain() to use DSB_WAIT_FOR_VBLANK Ville Syrjala
2024-07-05 15:58 ` Manna, Animesh
2024-07-05 16:09 ` Manna, Animesh
2024-07-05 17:36 ` Ville Syrjälä
2024-07-05 17:39 ` Ville Syrjälä
2024-08-21 14:58 ` Manna, Animesh
2024-08-23 12:44 ` Ville Syrjälä
2024-08-27 6:23 ` Manna, Animesh
2024-06-24 19:10 ` [PATCH 12/14] drm/i915/dsb: Clear DSB_ENABLE_DEWAKE once the DSB is done Ville Syrjala
2024-07-05 17:26 ` Manna, Animesh
2024-06-24 19:10 ` [PATCH 13/14] drm/i915/dsb: s/dsb/dsb_color_vblank/ Ville Syrjala
2024-07-05 17:28 ` Manna, Animesh
2024-06-24 19:10 ` [PATCH 14/14] drm/i915/dsb: Use chained DSBs for LUT programming Ville Syrjala
2024-08-27 6:25 ` Manna, Animesh
2024-06-24 19:54 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2024-06-24 19:54 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-06-24 20:01 ` ✓ Fi.CI.BAT: success " Patchwork
2024-06-25 14:42 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsb: Use chained DSBs for LUT programming (rev2) Patchwork
2024-06-25 14:42 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-06-25 14:55 ` ✓ Fi.CI.BAT: success " Patchwork
2024-06-26 2:30 ` ✗ Fi.CI.IGT: failure for drm/i915/dsb: Use chained DSBs for LUT programming Patchwork
2024-06-26 9:57 ` ✗ Fi.CI.IGT: failure for drm/i915/dsb: Use chained DSBs for LUT programming (rev2) Patchwork
2024-08-28 12:06 ` ✗ Fi.CI.BUILD: warning for drm/i915/dsb: Use chained DSBs for LUT programming (rev3) Patchwork
2024-08-28 12:06 ` ✗ Fi.CI.CHECKPATCH: " Patchwork
2024-08-28 12:07 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-08-28 12:27 ` ✓ Fi.CI.BAT: success " Patchwork
2024-08-29 8:56 ` ✗ Fi.CI.IGT: failure " Patchwork
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