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From: Sunil V L <sunilvl@ventanamicro.com>
To: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	rafael.j.wysocki@intel.com, ajones@ventanamicro.com,
	conor.dooley@microchip.com, aou@eecs.berkeley.edu,
	palmer@dabbelt.com, paul.walmsley@sifive.com
Subject: Re: [PATCH v2 1/1] RISC-V: ACPI: Enable SPCR table for console output on RISC-V
Date: Tue, 9 Jul 2024 10:19:50 +0530	[thread overview]
Message-ID: <ZozBbibw+CyYsqeR@sunil-laptop> (raw)
In-Reply-To: <20240502073751.102093-2-jeeheng.sia@starfivetech.com>

On Thu, May 02, 2024 at 12:37:51AM -0700, Sia Jee Heng wrote:
> The ACPI SPCR code has been used to enable console output for ARM64 and
> X86. The same code can be reused for RISC-V. Furthermore, SPCR table is
> mandated for headless system as outlined in the RISC-V BRS
> Specification, chapter 6.
> 
> Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
> ---
>  arch/riscv/Kconfig       |  1 +
>  arch/riscv/kernel/acpi.c | 12 +++++++++++-
>  2 files changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index be09c8836d56..ff2e270bbe01 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -14,6 +14,7 @@ config RISCV
>  	def_bool y
>  	select ACPI_GENERIC_GSI if ACPI
>  	select ACPI_REDUCED_HARDWARE_ONLY if ACPI
> +	select ACPI_SPCR_TABLE if ACPI
>  	select ARCH_DMA_DEFAULT_COHERENT
>  	select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
>  	select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
> diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c
> index e619edc8b0cc..43a12c00ae8b 100644
> --- a/arch/riscv/kernel/acpi.c
> +++ b/arch/riscv/kernel/acpi.c
> @@ -17,7 +17,9 @@
>  #include <linux/efi.h>
>  #include <linux/io.h>
>  #include <linux/memblock.h>
> +#include <linux/of_fdt.h>
>  #include <linux/pci.h>
> +#include <linux/serial_core.h>
>  
>  int acpi_noirq = 1;		/* skip ACPI IRQ initialization */
>  int acpi_disabled = 1;
> @@ -131,7 +133,7 @@ void __init acpi_boot_table_init(void)
>  	if (param_acpi_off ||
>  	    (!param_acpi_on && !param_acpi_force &&
>  	     efi.acpi20 == EFI_INVALID_TABLE_ADDR))
> -		return;
> +		goto done;
>  
>  	/*
>  	 * ACPI is disabled at this point. Enable it in order to parse
> @@ -151,6 +153,14 @@ void __init acpi_boot_table_init(void)
>  		if (!param_acpi_force)
>  			disable_acpi();
>  	}
> +
> +done:
> +	if (acpi_disabled) {
> +		if (earlycon_acpi_spcr_enable)
> +			early_init_dt_scan_chosen_stdout();
> +	} else {
> +		acpi_parse_spcr(earlycon_acpi_spcr_enable, true);
> +	}
LGTM.

Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>

Thanks,
Sunil
>  }
>  
>  static int acpi_parse_madt_rintc(union acpi_subtable_headers *header, const unsigned long end)
> -- 
> 2.34.1
> 

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linux-riscv@lists.infradead.org
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WARNING: multiple messages have this Message-ID (diff)
From: Sunil V L <sunilvl@ventanamicro.com>
To: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	rafael.j.wysocki@intel.com, ajones@ventanamicro.com,
	conor.dooley@microchip.com, aou@eecs.berkeley.edu,
	palmer@dabbelt.com, paul.walmsley@sifive.com
Subject: Re: [PATCH v2 1/1] RISC-V: ACPI: Enable SPCR table for console output on RISC-V
Date: Tue, 9 Jul 2024 10:19:50 +0530	[thread overview]
Message-ID: <ZozBbibw+CyYsqeR@sunil-laptop> (raw)
In-Reply-To: <20240502073751.102093-2-jeeheng.sia@starfivetech.com>

On Thu, May 02, 2024 at 12:37:51AM -0700, Sia Jee Heng wrote:
> The ACPI SPCR code has been used to enable console output for ARM64 and
> X86. The same code can be reused for RISC-V. Furthermore, SPCR table is
> mandated for headless system as outlined in the RISC-V BRS
> Specification, chapter 6.
> 
> Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
> ---
>  arch/riscv/Kconfig       |  1 +
>  arch/riscv/kernel/acpi.c | 12 +++++++++++-
>  2 files changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index be09c8836d56..ff2e270bbe01 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -14,6 +14,7 @@ config RISCV
>  	def_bool y
>  	select ACPI_GENERIC_GSI if ACPI
>  	select ACPI_REDUCED_HARDWARE_ONLY if ACPI
> +	select ACPI_SPCR_TABLE if ACPI
>  	select ARCH_DMA_DEFAULT_COHERENT
>  	select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
>  	select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
> diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c
> index e619edc8b0cc..43a12c00ae8b 100644
> --- a/arch/riscv/kernel/acpi.c
> +++ b/arch/riscv/kernel/acpi.c
> @@ -17,7 +17,9 @@
>  #include <linux/efi.h>
>  #include <linux/io.h>
>  #include <linux/memblock.h>
> +#include <linux/of_fdt.h>
>  #include <linux/pci.h>
> +#include <linux/serial_core.h>
>  
>  int acpi_noirq = 1;		/* skip ACPI IRQ initialization */
>  int acpi_disabled = 1;
> @@ -131,7 +133,7 @@ void __init acpi_boot_table_init(void)
>  	if (param_acpi_off ||
>  	    (!param_acpi_on && !param_acpi_force &&
>  	     efi.acpi20 == EFI_INVALID_TABLE_ADDR))
> -		return;
> +		goto done;
>  
>  	/*
>  	 * ACPI is disabled at this point. Enable it in order to parse
> @@ -151,6 +153,14 @@ void __init acpi_boot_table_init(void)
>  		if (!param_acpi_force)
>  			disable_acpi();
>  	}
> +
> +done:
> +	if (acpi_disabled) {
> +		if (earlycon_acpi_spcr_enable)
> +			early_init_dt_scan_chosen_stdout();
> +	} else {
> +		acpi_parse_spcr(earlycon_acpi_spcr_enable, true);
> +	}
LGTM.

Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>

Thanks,
Sunil
>  }
>  
>  static int acpi_parse_madt_rintc(union acpi_subtable_headers *header, const unsigned long end)
> -- 
> 2.34.1
> 

  reply	other threads:[~2024-07-09  4:50 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-05-02  7:37 [PATCH v2 0/1] Enable SPCR table for console output on RISC-V Sia Jee Heng
2024-05-02  7:37 ` Sia Jee Heng
2024-05-02  7:37 ` [PATCH v2 1/1] RISC-V: ACPI: " Sia Jee Heng
2024-05-02  7:37   ` Sia Jee Heng
2024-07-09  4:49   ` Sunil V L [this message]
2024-07-09  4:49     ` Sunil V L
2024-07-25 13:20 ` [PATCH v2 0/1] " patchwork-bot+linux-riscv
2024-07-25 13:20   ` patchwork-bot+linux-riscv

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