From: Charlie Jenkins <charlie@rivosinc.com>
To: Jesse Taube <jesse@rivosinc.com>
Cc: linux-riscv@lists.infradead.org,
"Jonathan Corbet" <corbet@lwn.net>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Conor Dooley" <conor@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Clément Léger" <cleger@rivosinc.com>,
"Evan Green" <evan@rivosinc.com>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Xiao Wang" <xiao.w.wang@intel.com>,
"Andy Chiu" <andy.chiu@sifive.com>,
"Eric Biggers" <ebiggers@google.com>,
"Greentime Hu" <greentime.hu@sifive.com>,
"Björn Töpel" <bjorn@rivosinc.com>,
"Heiko Stuebner" <heiko@sntech.de>,
"Costa Shulyupin" <costa.shul@redhat.com>,
"Andrew Morton" <akpm@linux-foundation.org>,
"Baoquan He" <bhe@redhat.com>,
"Anup Patel" <apatel@ventanamicro.com>,
"Zong Li" <zong.li@sifive.com>,
"Sami Tolvanen" <samitolvanen@google.com>,
"Ben Dooks" <ben.dooks@codethink.co.uk>,
"Alexandre Ghiti" <alexghiti@rivosinc.com>,
"Gustavo A. R. Silva" <gustavoars@kernel.org>,
"Erick Archer" <erick.archer@gmx.com>,
"Joel Granados" <j.granados@samsung.com>,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, stable@vger.kernel.org
Subject: Re: [PATCH v4 3/7] RISC-V: Check scalar unaligned access on all CPUs
Date: Thu, 11 Jul 2024 15:38:40 -0700 [thread overview]
Message-ID: <ZpBe8ECHxJ9QXVB2@ghost> (raw)
In-Reply-To: <20240711215846.834365-4-jesse@rivosinc.com>
On Thu, Jul 11, 2024 at 05:58:42PM -0400, Jesse Taube wrote:
> Originally, the check_unaligned_access_emulated_all_cpus function
> only checked the boot hart. This fixes the function to check all
> harts.
>
> Fixes: 71c54b3d169d ("riscv: report misaligned accesses emulation to hwprobe")
> Signed-off-by: Jesse Taube <jesse@rivosinc.com>
> Cc: stable@vger.kernel.org
> ---
> V1 -> V2:
> - New patch
> V2 -> V3:
> - Split patch
> V3 -> V4:
> - Re-add check for a system where a heterogeneous
> CPU is hotplugged into a previously homogenous
> system.
> ---
> arch/riscv/kernel/traps_misaligned.c | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
> index b62d5a2f4541..1a1bb41472ea 100644
> --- a/arch/riscv/kernel/traps_misaligned.c
> +++ b/arch/riscv/kernel/traps_misaligned.c
> @@ -526,11 +526,11 @@ int handle_misaligned_store(struct pt_regs *regs)
> return 0;
> }
>
> -static bool check_unaligned_access_emulated(int cpu)
> +static void check_unaligned_access_emulated(struct work_struct *unused)
Small change, can you give this a different name like "work" and instead
give it the attribute "__always_unused" like:
struct work_struct *work __always_unused
Otherwise,
Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
> {
> + int cpu = smp_processor_id();
> long *mas_ptr = per_cpu_ptr(&misaligned_access_speed, cpu);
> unsigned long tmp_var, tmp_val;
> - bool misaligned_emu_detected;
>
> *mas_ptr = RISCV_HWPROBE_MISALIGNED_UNKNOWN;
>
> @@ -538,19 +538,16 @@ static bool check_unaligned_access_emulated(int cpu)
> " "REG_L" %[tmp], 1(%[ptr])\n"
> : [tmp] "=r" (tmp_val) : [ptr] "r" (&tmp_var) : "memory");
>
> - misaligned_emu_detected = (*mas_ptr == RISCV_HWPROBE_MISALIGNED_EMULATED);
> /*
> * If unaligned_ctl is already set, this means that we detected that all
> * CPUS uses emulated misaligned access at boot time. If that changed
> * when hotplugging the new cpu, this is something we don't handle.
> */
> - if (unlikely(unaligned_ctl && !misaligned_emu_detected)) {
> + if (unlikely(unaligned_ctl && (*mas_ptr != RISCV_HWPROBE_MISALIGNED_EMULATED))) {
> pr_crit("CPU misaligned accesses non homogeneous (expected all emulated)\n");
> while (true)
> cpu_relax();
> }
> -
> - return misaligned_emu_detected;
> }
>
> bool check_unaligned_access_emulated_all_cpus(void)
> @@ -562,8 +559,11 @@ bool check_unaligned_access_emulated_all_cpus(void)
> * accesses emulated since tasks requesting such control can run on any
> * CPU.
> */
> + schedule_on_each_cpu(check_unaligned_access_emulated);
> +
> for_each_online_cpu(cpu)
> - if (!check_unaligned_access_emulated(cpu))
> + if (per_cpu(misaligned_access_speed, cpu)
> + != RISCV_HWPROBE_MISALIGNED_EMULATED)
> return false;
>
> unaligned_ctl = true;
> --
> 2.45.2
>
WARNING: multiple messages have this Message-ID (diff)
From: Charlie Jenkins <charlie@rivosinc.com>
To: Jesse Taube <jesse@rivosinc.com>
Cc: linux-riscv@lists.infradead.org,
"Jonathan Corbet" <corbet@lwn.net>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Conor Dooley" <conor@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Clément Léger" <cleger@rivosinc.com>,
"Evan Green" <evan@rivosinc.com>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Xiao Wang" <xiao.w.wang@intel.com>,
"Andy Chiu" <andy.chiu@sifive.com>,
"Eric Biggers" <ebiggers@google.com>,
"Greentime Hu" <greentime.hu@sifive.com>,
"Björn Töpel" <bjorn@rivosinc.com>,
"Heiko Stuebner" <heiko@sntech.de>,
"Costa Shulyupin" <costa.shul@redhat.com>,
"Andrew Morton" <akpm@linux-foundation.org>,
"Baoquan He" <bhe@redhat.com>,
"Anup Patel" <apatel@ventanamicro.com>,
"Zong Li" <zong.li@sifive.com>,
"Sami Tolvanen" <samitolvanen@google.com>,
"Ben Dooks" <ben.dooks@codethink.co.uk>,
"Alexandre Ghiti" <alexghiti@rivosinc.com>,
"Gustavo A. R. Silva" <gustavoars@kernel.org>,
"Erick Archer" <erick.archer@gmx.com>,
"Joel Granados" <j.granados@samsung.com>,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, stable@vger.kernel.org
Subject: Re: [PATCH v4 3/7] RISC-V: Check scalar unaligned access on all CPUs
Date: Thu, 11 Jul 2024 15:38:40 -0700 [thread overview]
Message-ID: <ZpBe8ECHxJ9QXVB2@ghost> (raw)
In-Reply-To: <20240711215846.834365-4-jesse@rivosinc.com>
On Thu, Jul 11, 2024 at 05:58:42PM -0400, Jesse Taube wrote:
> Originally, the check_unaligned_access_emulated_all_cpus function
> only checked the boot hart. This fixes the function to check all
> harts.
>
> Fixes: 71c54b3d169d ("riscv: report misaligned accesses emulation to hwprobe")
> Signed-off-by: Jesse Taube <jesse@rivosinc.com>
> Cc: stable@vger.kernel.org
> ---
> V1 -> V2:
> - New patch
> V2 -> V3:
> - Split patch
> V3 -> V4:
> - Re-add check for a system where a heterogeneous
> CPU is hotplugged into a previously homogenous
> system.
> ---
> arch/riscv/kernel/traps_misaligned.c | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
> index b62d5a2f4541..1a1bb41472ea 100644
> --- a/arch/riscv/kernel/traps_misaligned.c
> +++ b/arch/riscv/kernel/traps_misaligned.c
> @@ -526,11 +526,11 @@ int handle_misaligned_store(struct pt_regs *regs)
> return 0;
> }
>
> -static bool check_unaligned_access_emulated(int cpu)
> +static void check_unaligned_access_emulated(struct work_struct *unused)
Small change, can you give this a different name like "work" and instead
give it the attribute "__always_unused" like:
struct work_struct *work __always_unused
Otherwise,
Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
> {
> + int cpu = smp_processor_id();
> long *mas_ptr = per_cpu_ptr(&misaligned_access_speed, cpu);
> unsigned long tmp_var, tmp_val;
> - bool misaligned_emu_detected;
>
> *mas_ptr = RISCV_HWPROBE_MISALIGNED_UNKNOWN;
>
> @@ -538,19 +538,16 @@ static bool check_unaligned_access_emulated(int cpu)
> " "REG_L" %[tmp], 1(%[ptr])\n"
> : [tmp] "=r" (tmp_val) : [ptr] "r" (&tmp_var) : "memory");
>
> - misaligned_emu_detected = (*mas_ptr == RISCV_HWPROBE_MISALIGNED_EMULATED);
> /*
> * If unaligned_ctl is already set, this means that we detected that all
> * CPUS uses emulated misaligned access at boot time. If that changed
> * when hotplugging the new cpu, this is something we don't handle.
> */
> - if (unlikely(unaligned_ctl && !misaligned_emu_detected)) {
> + if (unlikely(unaligned_ctl && (*mas_ptr != RISCV_HWPROBE_MISALIGNED_EMULATED))) {
> pr_crit("CPU misaligned accesses non homogeneous (expected all emulated)\n");
> while (true)
> cpu_relax();
> }
> -
> - return misaligned_emu_detected;
> }
>
> bool check_unaligned_access_emulated_all_cpus(void)
> @@ -562,8 +559,11 @@ bool check_unaligned_access_emulated_all_cpus(void)
> * accesses emulated since tasks requesting such control can run on any
> * CPU.
> */
> + schedule_on_each_cpu(check_unaligned_access_emulated);
> +
> for_each_online_cpu(cpu)
> - if (!check_unaligned_access_emulated(cpu))
> + if (per_cpu(misaligned_access_speed, cpu)
> + != RISCV_HWPROBE_MISALIGNED_EMULATED)
> return false;
>
> unaligned_ctl = true;
> --
> 2.45.2
>
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next prev parent reply other threads:[~2024-07-11 22:38 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-11 21:58 [PATCH v4 0/7] RISC-V: Detect and report speed of unaligned vector accesses Jesse Taube
2024-07-11 21:58 ` Jesse Taube
2024-07-11 21:58 ` [PATCH v4 1/7] RISC-V: Add Zicclsm to cpufeature and hwprobe Jesse Taube
2024-07-11 21:58 ` Jesse Taube
2024-07-11 21:58 ` [PATCH v4 2/7] dt-bindings: riscv: Add Zicclsm ISA extension description Jesse Taube
2024-07-11 21:58 ` Jesse Taube
2024-07-11 21:58 ` [PATCH v4 3/7] RISC-V: Check scalar unaligned access on all CPUs Jesse Taube
2024-07-11 21:58 ` Jesse Taube
2024-07-11 22:38 ` Charlie Jenkins [this message]
2024-07-11 22:38 ` Charlie Jenkins
2024-07-11 21:58 ` [PATCH v4 4/7] RISC-V: Replace RISCV_MISALIGNED with RISCV_SCALAR_MISALIGNED Jesse Taube
2024-07-11 21:58 ` Jesse Taube
2024-07-11 22:39 ` Charlie Jenkins
2024-07-11 22:39 ` Charlie Jenkins
2024-07-11 21:58 ` [PATCH v4 5/7] RISC-V: Detect unaligned vector accesses supported Jesse Taube
2024-07-11 21:58 ` Jesse Taube
2024-07-11 22:46 ` Charlie Jenkins
2024-07-11 22:46 ` Charlie Jenkins
2024-07-11 21:58 ` [PATCH v4 6/7] RISC-V: Report vector unaligned access speed hwprobe Jesse Taube
2024-07-11 21:58 ` Jesse Taube
2024-07-11 22:48 ` Charlie Jenkins
2024-07-11 22:48 ` Charlie Jenkins
2024-07-11 21:58 ` [PATCH v4 7/7] RISC-V: hwprobe: Document unaligned vector perf key Jesse Taube
2024-07-11 21:58 ` Jesse Taube
2024-07-11 22:23 ` Charlie Jenkins
2024-07-11 22:23 ` Charlie Jenkins
2024-07-11 22:32 ` [PATCH v4 0/7] RISC-V: Detect and report speed of unaligned vector accesses Charlie Jenkins
2024-07-11 22:32 ` Charlie Jenkins
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