From: Andrea Parri <parri.andrea@gmail.com>
To: Alexandre Ghiti <alexghiti@rivosinc.com>
Cc: Jonathan Corbet <corbet@lwn.net>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Conor Dooley <conor@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Nathan Chancellor <nathan@kernel.org>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>, Will Deacon <will@kernel.org>,
Waiman Long <longman@redhat.com>,
Boqun Feng <boqun.feng@gmail.com>, Arnd Bergmann <arnd@arndb.de>,
Leonardo Bras <leobras@redhat.com>, Guo Ren <guoren@kernel.org>,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-arch@vger.kernel.org
Subject: Re: [PATCH v3 11/11] riscv: Add qspinlock support
Date: Wed, 17 Jul 2024 18:29:06 +0200 [thread overview]
Message-ID: <ZpfxUvIx+0ClOqCc@andrea> (raw)
In-Reply-To: <20240717061957.140712-12-alexghiti@rivosinc.com>
> +config RISCV_QUEUED_SPINLOCKS
I'm seeing the following warnings with CONFIG_RISCV_QUEUED_SPINLOCKS=y:
In file included from ./arch/riscv/include/generated/asm/qspinlock.h:1,
from kernel/locking/qspinlock.c:24:
./include/asm-generic/qspinlock.h:144:9: warning: "arch_spin_is_locked" redefined
144 | #define arch_spin_is_locked(l) queued_spin_is_locked(l)
| ^~~~~~~~~~~~~~~~~~~
In file included from ./arch/riscv/include/generated/asm/ticket_spinlock.h:1,
from ./arch/riscv/include/asm/spinlock.h:33,
from ./include/linux/spinlock.h:95,
from ./include/linux/sched.h:2142,
from ./include/linux/percpu.h:13,
from kernel/locking/qspinlock.c:19:
./include/asm-generic/ticket_spinlock.h:97:9: note: this is the location of the previous definition
97 | #define arch_spin_is_locked(l) ticket_spin_is_locked(l)
| ^~~~~~~~~~~~~~~~~~~
./include/asm-generic/qspinlock.h:145:9: warning: "arch_spin_is_contended" redefined
145 | #define arch_spin_is_contended(l) queued_spin_is_contended(l)
| ^~~~~~~~~~~~~~~~~~~~~~
./include/asm-generic/ticket_spinlock.h:98:9: note: this is the location of the previous definition
98 | #define arch_spin_is_contended(l) ticket_spin_is_contended(l)
| ^~~~~~~~~~~~~~~~~~~~~~
./include/asm-generic/qspinlock.h:146:9: warning: "arch_spin_value_unlocked" redefined
146 | #define arch_spin_value_unlocked(l) queued_spin_value_unlocked(l)
| ^~~~~~~~~~~~~~~~~~~~~~~~
./include/asm-generic/ticket_spinlock.h:99:9: note: this is the location of the previous definition
99 | #define arch_spin_value_unlocked(l) ticket_spin_value_unlocked(l)
| ^~~~~~~~~~~~~~~~~~~~~~~~
./include/asm-generic/qspinlock.h:147:9: warning: "arch_spin_lock" redefined
147 | #define arch_spin_lock(l) queued_spin_lock(l)
| ^~~~~~~~~~~~~~
./include/asm-generic/ticket_spinlock.h:100:9: note: this is the location of the previous definition
100 | #define arch_spin_lock(l) ticket_spin_lock(l)
| ^~~~~~~~~~~~~~
./include/asm-generic/qspinlock.h:148:9: warning: "arch_spin_trylock" redefined
148 | #define arch_spin_trylock(l) queued_spin_trylock(l)
| ^~~~~~~~~~~~~~~~~
./include/asm-generic/ticket_spinlock.h:101:9: note: this is the location of the previous definition
101 | #define arch_spin_trylock(l) ticket_spin_trylock(l)
| ^~~~~~~~~~~~~~~~~
./include/asm-generic/qspinlock.h:149:9: warning: "arch_spin_unlock" redefined
149 | #define arch_spin_unlock(l) queued_spin_unlock(l)
| ^~~~~~~~~~~~~~~~
./include/asm-generic/ticket_spinlock.h:102:9: note: this is the location of the previous definition
102 | #define arch_spin_unlock(l) ticket_spin_unlock(l)
The following diff resolves them for me (please double check):
diff --git a/arch/riscv/include/asm/spinlock.h b/arch/riscv/include/asm/spinlock.h
index 4856d50006f28..2d59f56a9e2d1 100644
--- a/arch/riscv/include/asm/spinlock.h
+++ b/arch/riscv/include/asm/spinlock.h
@@ -30,7 +30,11 @@ SPINLOCK_BASE_DECLARE(value_unlocked, int, arch_spinlock_t)
#else
+#if defined(CONFIG_RISCV_TICKET_SPINLOCKS)
#include <asm/ticket_spinlock.h>
+#elif defined(CONFIG_RISCV_QUEUED_SPINLOCKS)
+#include <asm/qspinlock.h>
+#endif
#endif
> +DEFINE_STATIC_KEY_TRUE(qspinlock_key);
> +EXPORT_SYMBOL(qspinlock_key);
> +
> +static void __init riscv_spinlock_init(void)
> +{
> + char *using_ext;
> +
> + if (IS_ENABLED(CONFIG_RISCV_ISA_ZACAS) &&
> + IS_ENABLED(CONFIG_RISCV_ISA_ZABHA)) {
> + using_ext = "using Zabha";
> +
> + asm goto(ALTERNATIVE("j %[no_zacas]", "nop", 0, RISCV_ISA_EXT_ZACAS, 1)
> + : : : : no_zacas);
> + asm goto(ALTERNATIVE("nop", "j %[qspinlock]", 0, RISCV_ISA_EXT_ZABHA, 1)
> + : : : : qspinlock);
> + }
> +
> +no_zacas:
> + using_ext = "using Ziccrse";
> + asm goto(ALTERNATIVE("nop", "j %[qspinlock]", 0,
> + RISCV_ISA_EXT_ZICCRSE, 1)
> + : : : : qspinlock);
> +
> + static_branch_disable(&qspinlock_key);
> + pr_info("Ticket spinlock: enabled\n");
> +
> + return;
> +
> +qspinlock:
> + pr_info("Queued spinlock %s: enabled\n", using_ext);
> +}
> +
Your commit message suggests that riscv_spinlock_init() doesn't need to
do anything if CONFIG_RISCV_COMBO_SPINLOCKS=n:
diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
index d7c31c9b8ead2..b2be1b0b700d2 100644
--- a/arch/riscv/kernel/setup.c
+++ b/arch/riscv/kernel/setup.c
@@ -244,6 +244,7 @@ static void __init parse_dtb(void)
#endif
}
+#if defined(CONFIG_RISCV_COMBO_SPINLOCKS)
DEFINE_STATIC_KEY_TRUE(qspinlock_key);
EXPORT_SYMBOL(qspinlock_key);
@@ -275,6 +276,11 @@ static void __init riscv_spinlock_init(void)
qspinlock:
pr_info("Queued spinlock %s: enabled\n", using_ext);
}
+#else
+static void __init riscv_spinlock_init(void)
+{
+}
+#endif
extern void __init init_rt_signal_env(void);
Makes sense? What am I missing?
Andrea
WARNING: multiple messages have this Message-ID (diff)
From: Andrea Parri <parri.andrea@gmail.com>
To: Alexandre Ghiti <alexghiti@rivosinc.com>
Cc: Jonathan Corbet <corbet@lwn.net>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Conor Dooley <conor@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Nathan Chancellor <nathan@kernel.org>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>, Will Deacon <will@kernel.org>,
Waiman Long <longman@redhat.com>,
Boqun Feng <boqun.feng@gmail.com>, Arnd Bergmann <arnd@arndb.de>,
Leonardo Bras <leobras@redhat.com>, Guo Ren <guoren@kernel.org>,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-arch@vger.kernel.org
Subject: Re: [PATCH v3 11/11] riscv: Add qspinlock support
Date: Wed, 17 Jul 2024 18:29:06 +0200 [thread overview]
Message-ID: <ZpfxUvIx+0ClOqCc@andrea> (raw)
In-Reply-To: <20240717061957.140712-12-alexghiti@rivosinc.com>
> +config RISCV_QUEUED_SPINLOCKS
I'm seeing the following warnings with CONFIG_RISCV_QUEUED_SPINLOCKS=y:
In file included from ./arch/riscv/include/generated/asm/qspinlock.h:1,
from kernel/locking/qspinlock.c:24:
./include/asm-generic/qspinlock.h:144:9: warning: "arch_spin_is_locked" redefined
144 | #define arch_spin_is_locked(l) queued_spin_is_locked(l)
| ^~~~~~~~~~~~~~~~~~~
In file included from ./arch/riscv/include/generated/asm/ticket_spinlock.h:1,
from ./arch/riscv/include/asm/spinlock.h:33,
from ./include/linux/spinlock.h:95,
from ./include/linux/sched.h:2142,
from ./include/linux/percpu.h:13,
from kernel/locking/qspinlock.c:19:
./include/asm-generic/ticket_spinlock.h:97:9: note: this is the location of the previous definition
97 | #define arch_spin_is_locked(l) ticket_spin_is_locked(l)
| ^~~~~~~~~~~~~~~~~~~
./include/asm-generic/qspinlock.h:145:9: warning: "arch_spin_is_contended" redefined
145 | #define arch_spin_is_contended(l) queued_spin_is_contended(l)
| ^~~~~~~~~~~~~~~~~~~~~~
./include/asm-generic/ticket_spinlock.h:98:9: note: this is the location of the previous definition
98 | #define arch_spin_is_contended(l) ticket_spin_is_contended(l)
| ^~~~~~~~~~~~~~~~~~~~~~
./include/asm-generic/qspinlock.h:146:9: warning: "arch_spin_value_unlocked" redefined
146 | #define arch_spin_value_unlocked(l) queued_spin_value_unlocked(l)
| ^~~~~~~~~~~~~~~~~~~~~~~~
./include/asm-generic/ticket_spinlock.h:99:9: note: this is the location of the previous definition
99 | #define arch_spin_value_unlocked(l) ticket_spin_value_unlocked(l)
| ^~~~~~~~~~~~~~~~~~~~~~~~
./include/asm-generic/qspinlock.h:147:9: warning: "arch_spin_lock" redefined
147 | #define arch_spin_lock(l) queued_spin_lock(l)
| ^~~~~~~~~~~~~~
./include/asm-generic/ticket_spinlock.h:100:9: note: this is the location of the previous definition
100 | #define arch_spin_lock(l) ticket_spin_lock(l)
| ^~~~~~~~~~~~~~
./include/asm-generic/qspinlock.h:148:9: warning: "arch_spin_trylock" redefined
148 | #define arch_spin_trylock(l) queued_spin_trylock(l)
| ^~~~~~~~~~~~~~~~~
./include/asm-generic/ticket_spinlock.h:101:9: note: this is the location of the previous definition
101 | #define arch_spin_trylock(l) ticket_spin_trylock(l)
| ^~~~~~~~~~~~~~~~~
./include/asm-generic/qspinlock.h:149:9: warning: "arch_spin_unlock" redefined
149 | #define arch_spin_unlock(l) queued_spin_unlock(l)
| ^~~~~~~~~~~~~~~~
./include/asm-generic/ticket_spinlock.h:102:9: note: this is the location of the previous definition
102 | #define arch_spin_unlock(l) ticket_spin_unlock(l)
The following diff resolves them for me (please double check):
diff --git a/arch/riscv/include/asm/spinlock.h b/arch/riscv/include/asm/spinlock.h
index 4856d50006f28..2d59f56a9e2d1 100644
--- a/arch/riscv/include/asm/spinlock.h
+++ b/arch/riscv/include/asm/spinlock.h
@@ -30,7 +30,11 @@ SPINLOCK_BASE_DECLARE(value_unlocked, int, arch_spinlock_t)
#else
+#if defined(CONFIG_RISCV_TICKET_SPINLOCKS)
#include <asm/ticket_spinlock.h>
+#elif defined(CONFIG_RISCV_QUEUED_SPINLOCKS)
+#include <asm/qspinlock.h>
+#endif
#endif
> +DEFINE_STATIC_KEY_TRUE(qspinlock_key);
> +EXPORT_SYMBOL(qspinlock_key);
> +
> +static void __init riscv_spinlock_init(void)
> +{
> + char *using_ext;
> +
> + if (IS_ENABLED(CONFIG_RISCV_ISA_ZACAS) &&
> + IS_ENABLED(CONFIG_RISCV_ISA_ZABHA)) {
> + using_ext = "using Zabha";
> +
> + asm goto(ALTERNATIVE("j %[no_zacas]", "nop", 0, RISCV_ISA_EXT_ZACAS, 1)
> + : : : : no_zacas);
> + asm goto(ALTERNATIVE("nop", "j %[qspinlock]", 0, RISCV_ISA_EXT_ZABHA, 1)
> + : : : : qspinlock);
> + }
> +
> +no_zacas:
> + using_ext = "using Ziccrse";
> + asm goto(ALTERNATIVE("nop", "j %[qspinlock]", 0,
> + RISCV_ISA_EXT_ZICCRSE, 1)
> + : : : : qspinlock);
> +
> + static_branch_disable(&qspinlock_key);
> + pr_info("Ticket spinlock: enabled\n");
> +
> + return;
> +
> +qspinlock:
> + pr_info("Queued spinlock %s: enabled\n", using_ext);
> +}
> +
Your commit message suggests that riscv_spinlock_init() doesn't need to
do anything if CONFIG_RISCV_COMBO_SPINLOCKS=n:
diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
index d7c31c9b8ead2..b2be1b0b700d2 100644
--- a/arch/riscv/kernel/setup.c
+++ b/arch/riscv/kernel/setup.c
@@ -244,6 +244,7 @@ static void __init parse_dtb(void)
#endif
}
+#if defined(CONFIG_RISCV_COMBO_SPINLOCKS)
DEFINE_STATIC_KEY_TRUE(qspinlock_key);
EXPORT_SYMBOL(qspinlock_key);
@@ -275,6 +276,11 @@ static void __init riscv_spinlock_init(void)
qspinlock:
pr_info("Queued spinlock %s: enabled\n", using_ext);
}
+#else
+static void __init riscv_spinlock_init(void)
+{
+}
+#endif
extern void __init init_rt_signal_env(void);
Makes sense? What am I missing?
Andrea
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next prev parent reply other threads:[~2024-07-17 16:29 UTC|newest]
Thread overview: 80+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-17 6:19 [PATCH v3 00/11] Zacas/Zabha support and qspinlocks Alexandre Ghiti
2024-07-17 6:19 ` Alexandre Ghiti
2024-07-17 6:19 ` [PATCH v3 01/11] riscv: Implement cmpxchg32/64() using Zacas Alexandre Ghiti
2024-07-17 6:19 ` Alexandre Ghiti
2024-07-17 15:08 ` Andrew Jones
2024-07-17 15:08 ` Andrew Jones
2024-07-17 15:18 ` Alexandre Ghiti
2024-07-17 15:18 ` Alexandre Ghiti
2024-07-19 0:45 ` Samuel Holland
2024-07-19 0:45 ` Samuel Holland
2024-07-19 11:48 ` Alexandre Ghiti
2024-07-19 11:48 ` Alexandre Ghiti
2024-07-19 11:53 ` Alexandre Ghiti
2024-07-19 11:53 ` Alexandre Ghiti
2024-07-17 6:19 ` [PATCH v3 02/11] dt-bindings: riscv: Add Zabha ISA extension description Alexandre Ghiti
2024-07-17 6:19 ` Alexandre Ghiti
2024-07-17 6:42 ` Krzysztof Kozlowski
2024-07-17 6:42 ` Krzysztof Kozlowski
2024-07-17 9:32 ` Guo Ren
2024-07-17 9:32 ` Guo Ren
2024-07-17 6:19 ` [PATCH v3 03/11] riscv: Implement cmpxchg8/16() using Zabha Alexandre Ghiti
2024-07-17 6:19 ` Alexandre Ghiti
2024-07-17 15:26 ` Andrew Jones
2024-07-17 15:26 ` Andrew Jones
2024-07-17 15:29 ` Conor Dooley
2024-07-17 15:29 ` Conor Dooley
2024-07-17 15:34 ` Alexandre Ghiti
2024-07-17 15:34 ` Alexandre Ghiti
2024-07-18 12:50 ` Alexandre Ghiti
2024-07-18 12:50 ` Alexandre Ghiti
2024-07-18 16:06 ` Andrew Jones
2024-07-18 16:06 ` Andrew Jones
2024-07-18 16:20 ` Alexandre Ghiti
2024-07-18 16:20 ` Alexandre Ghiti
2024-07-17 6:19 ` [PATCH v3 04/11] riscv: Improve zacas fully-ordered cmpxchg() Alexandre Ghiti
2024-07-17 6:19 ` Alexandre Ghiti
2024-07-17 6:19 ` [PATCH v3 05/11] riscv: Implement arch_cmpxchg128() using Zacas Alexandre Ghiti
2024-07-17 6:19 ` Alexandre Ghiti
2024-07-17 20:34 ` Andrew Jones
2024-07-17 20:34 ` Andrew Jones
2024-07-18 7:48 ` Alexandre Ghiti
2024-07-18 7:48 ` Alexandre Ghiti
2024-07-18 8:33 ` Conor Dooley
2024-07-18 8:33 ` Conor Dooley
2024-07-18 9:35 ` Arnd Bergmann
2024-07-18 9:35 ` Arnd Bergmann
2024-07-17 6:19 ` [PATCH v3 06/11] riscv: Implement xchg8/16() using Zabha Alexandre Ghiti
2024-07-17 6:19 ` Alexandre Ghiti
2024-07-17 6:19 ` [PATCH v3 07/11] asm-generic: ticket-lock: Reuse arch_spinlock_t of qspinlock Alexandre Ghiti
2024-07-17 6:19 ` Alexandre Ghiti
2024-07-17 6:19 ` [PATCH v3 08/11] asm-generic: ticket-lock: Add separate ticket-lock.h Alexandre Ghiti
2024-07-17 6:19 ` Alexandre Ghiti
2024-07-17 6:19 ` [PATCH v3 09/11] riscv: Add ISA extension parsing for Ziccrse Alexandre Ghiti
2024-07-17 6:19 ` Alexandre Ghiti
2024-07-19 0:53 ` Samuel Holland
2024-07-19 0:53 ` Samuel Holland
2024-07-19 9:11 ` Alexandre Ghiti
2024-07-19 9:11 ` Alexandre Ghiti
2024-07-17 6:19 ` [PATCH v3 10/11] dt-bindings: riscv: Add Ziccrse ISA extension description Alexandre Ghiti
2024-07-17 6:19 ` Alexandre Ghiti
2024-07-17 6:55 ` Krzysztof Kozlowski
2024-07-17 6:55 ` Krzysztof Kozlowski
2024-07-17 9:42 ` Guo Ren
2024-07-17 9:42 ` Guo Ren
2024-07-17 6:19 ` [PATCH v3 11/11] riscv: Add qspinlock support Alexandre Ghiti
2024-07-17 6:19 ` Alexandre Ghiti
2024-07-17 9:30 ` Guo Ren
2024-07-17 9:30 ` Guo Ren
2024-07-18 13:11 ` Alexandre Ghiti
2024-07-18 13:11 ` Alexandre Ghiti
2024-07-17 16:29 ` Andrea Parri [this message]
2024-07-17 16:29 ` Andrea Parri
2024-07-18 13:08 ` Alexandre Ghiti
2024-07-18 13:08 ` Alexandre Ghiti
2024-07-19 1:05 ` Samuel Holland
2024-07-19 1:05 ` Samuel Holland
2024-07-19 9:06 ` Alexandre Ghiti
2024-07-19 9:06 ` Alexandre Ghiti
2024-07-17 16:37 ` [PATCH v3 00/11] Zacas/Zabha support and qspinlocks Andrea Parri
2024-07-17 16:37 ` Andrea Parri
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