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From: Deepak Gupta <debug@rivosinc.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, palmer@dabbelt.com,
	Alistair.Francis@wdc.com, bmeng.cn@gmail.com,
	liwei1518@gmail.com, dbarboza@ventanamicro.com,
	zhiwei_liu@linux.alibaba.com, jim.shu@sifive.com,
	andy.chiu@sifive.com, kito.cheng@sifive.com
Subject: Re: [PATCH v9 03/17] target/riscv: save and restore elp state on priv transitions
Date: Mon, 26 Aug 2024 17:52:33 -0700	[thread overview]
Message-ID: <Zs0jURx7jbgd64jV@debug.ba.rivosinc.com> (raw)
In-Reply-To: <da021104-6836-4e5b-a8a4-991f975c553c@linaro.org>

On Tue, Aug 27, 2024 at 10:33:04AM +1000, Richard Henderson wrote:
>On 8/27/24 01:29, Deepak Gupta wrote:
>>diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>>index 8e1f05e5b1..083d405516 100644
>>--- a/target/riscv/cpu.c
>>+++ b/target/riscv/cpu.c
>>@@ -1022,6 +1022,11 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
>>      env->load_res = -1;
>>      set_default_nan_mode(1, &env->fp_status);
>>+#ifdef CONFIG_USER_ONLY
>>+    /* qemu-user for riscv, fcfi is off by default */
>>+    env->ufcfien = false;
>>+#endif
>...
>>@@ -226,6 +226,7 @@ struct CPUArchState {
>>      bool      elp;
>>  #ifdef CONFIG_USER_ONLY
>>      uint32_t elf_flags;
>>+    bool ufcfien;
>>  #endif
>
>Thinking about this more, I think adding separate controls for 
>user-only is a bad precedent to set.  You said you are adding these 
>because senvcfg/menvcfg are ifdefed: well, that should be the thing 
>that we fix.

If a binary is compiled with zicbo, it'll have those instructions in user
binary. I am not sure how those binaries will run on qemu-user (or if it was
tested with qemu-user)

In case of zicfilp + zicfiss we are runnning binaries compiled with zicfilp
and zicfiss with qemu-user and qemu-system both. Use of qemu-user to generate
traces for feeding into CPU modeling is quite useful. Thus mechanism to track
if landing pad and shadow stack is enabled for current user task (in case of
qemu-user) is very useful.

senvcfg and menvcfg belong to S and M state and don't actually mean anything
for qemu-user. However if that's how it is for arm as well (i.e. exposing system
state for qemu-user), then probably there is precedent.
But it looks like a much larger exercise to me.

>
>The only real user of *envcfg that I see so far is check_zicbo_envcfg, 
>which does not use the same switch statement as this:
>
>>+    switch (env->priv) {
>>+    case PRV_U:
>>+        if (riscv_has_ext(env, RVS)) {
>>+            return env->senvcfg & MENVCFG_LPE;
>>+        }
>>+        return env->menvcfg & MENVCFG_LPE;
>>+    case PRV_S:
>>+        if (env->virt_enabled) {
>>+            return env->henvcfg & HENVCFG_LPE;
>>+        }
>>+        return env->menvcfg & MENVCFG_LPE;
>>+    case PRV_M:
>>+        return env->mseccfg & MSECCFG_MLPE;
>>+    default:
>>+        g_assert_not_reached();
>>+    }
>
>I think your function should look more like check_zicbo_envcfg: (1) 
>PRV_U may be either U or VU, and different tests apply; (2) M-mode 
>disable means that no lower level may be enabled.

In case of landing pad, (2) doesn't hold true. Each mode can independently
enable landing pad for next lower mode even if it wasn't enabled for current
mode. Reason being that you can have a firmware which is still not landing pad
enabled and you would want to avoid landing pad related faults in M mode but
still want to make sure S mode and U mode can enable landing pad for themselves.
Same goes with respect to S mode, S mode can have its landing pad disabled while
it can enable landing pad for U mode.

Although logic for shadow stack enable is same as zicbo. Shadow stack enable requires
target software to opt-in by having instructions compiled in and doesn't impact 
behavior of existing instructions.

>
>It would be nice if you could generalize check_zicbo_envcfg to apply 
>to your new use as well.  Perhaps some tri-state function to say 
>"enabled", "disabled", "virtual disabled".

So while shadow stack and zicbo are similar in terms of enabling. Landing pad
enable differs. 

You still want me to generalize *envcfg flow?
>
>
>r~


  reply	other threads:[~2024-08-27  0:52 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-26 15:29 [PATCH v9 00/17] riscv support for control flow integrity extensions Deepak Gupta
2024-08-26 15:29 ` [PATCH v9 01/17] target/riscv: Add zicfilp extension Deepak Gupta
2024-08-27  2:16   ` Alistair Francis
2024-08-26 15:29 ` [PATCH v9 02/17] target/riscv: Introduce elp state and enabling controls for zicfilp Deepak Gupta
2024-08-27  2:58   ` Alistair Francis
2024-08-26 15:29 ` [PATCH v9 03/17] target/riscv: save and restore elp state on priv transitions Deepak Gupta
2024-08-27  0:33   ` Richard Henderson
2024-08-27  0:52     ` Deepak Gupta [this message]
2024-08-27  1:34       ` Richard Henderson
2024-08-27  3:53         ` Alistair Francis
2024-08-27  3:58           ` Richard Henderson
2024-08-27  4:03             ` Alistair Francis
2024-08-27  4:29               ` Richard Henderson
2024-08-27  5:47                 ` Alistair Francis
2024-08-26 15:29 ` [PATCH v9 04/17] target/riscv: additional code information for sw check Deepak Gupta
2024-08-27  3:55   ` Alistair Francis
2024-08-26 15:29 ` [PATCH v9 05/17] target/riscv: tracking indirect branches (fcfi) for zicfilp Deepak Gupta
2024-08-27  3:58   ` Alistair Francis
2024-08-26 15:29 ` [PATCH v9 06/17] target/riscv: zicfilp `lpad` impl and branch tracking Deepak Gupta
2024-08-27  4:14   ` Alistair Francis
2024-08-26 15:29 ` [PATCH v9 07/17] disas/riscv: enable `lpad` disassembly Deepak Gupta
2024-08-27  4:15   ` Alistair Francis
2024-08-26 15:29 ` [PATCH v9 08/17] target/riscv: Add zicfiss extension Deepak Gupta
2024-08-27  4:20   ` Alistair Francis
2024-08-26 15:29 ` [PATCH v9 09/17] target/riscv: introduce ssp and enabling controls for zicfiss Deepak Gupta
2024-08-26 15:29 ` [PATCH v9 10/17] target/riscv: tb flag for shadow stack instructions Deepak Gupta
2024-08-27  5:51   ` Alistair Francis
2024-08-26 15:29 ` [PATCH v9 11/17] target/riscv: mmu changes for zicfiss shadow stack protection Deepak Gupta
2024-08-27  5:59   ` Alistair Francis
2024-08-27 23:06     ` Deepak Gupta
2024-08-26 15:29 ` [PATCH v9 12/17] target/riscv: AMO operations always raise store/AMO fault Deepak Gupta
2024-08-27  0:34   ` Richard Henderson
2024-08-26 15:29 ` [PATCH v9 13/17] target/riscv: update `decode_save_opc` to store extra word2 Deepak Gupta
2024-08-27  0:35   ` Richard Henderson
2024-08-26 15:29 ` [PATCH v9 14/17] target/riscv: implement zicfiss instructions Deepak Gupta
2024-08-26 15:29 ` [PATCH v9 15/17] target/riscv: compressed encodings for sspush and sspopchk Deepak Gupta
2024-08-27  0:37   ` Richard Henderson
2024-08-26 15:29 ` [PATCH v9 16/17] disas/riscv: enable disassembly for zicfiss instructions Deepak Gupta
2024-08-26 15:29 ` [PATCH v9 17/17] disas/riscv: enable disassembly for compressed sspush/sspopchk Deepak Gupta
2024-08-27  2:44 ` [PATCH v9 00/17] riscv support for control flow integrity extensions Alistair Francis

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