From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Jani Nikula <jani.nikula@intel.com>
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Subject: Re: [PATCH 05/11] drm/i915/reg: fix SKL scaler register style
Date: Tue, 10 Sep 2024 00:01:07 +0300 [thread overview]
Message-ID: <Zt9iE9QFWI-3QfYW@intel.com> (raw)
In-Reply-To: <cff41ece4d6147314e731ac61e7bac06942d75cc.1725908152.git.jani.nikula@intel.com>
On Mon, Sep 09, 2024 at 09:58:56PM +0300, Jani Nikula wrote:
> Adhere to the style described at the top of i915_reg.h.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 64 ++++++++++++++++-----------------
> 1 file changed, 31 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9ece696baae8..2f09145b9791 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2229,11 +2229,15 @@
> /*
> * Skylake scalers
> */
> +#define _ID(id, a, b) _PICK_EVEN(id, a, b)
> #define _PS_1A_CTRL 0x68180
> #define _PS_2A_CTRL 0x68280
> #define _PS_1B_CTRL 0x68980
> #define _PS_2B_CTRL 0x68A80
> #define _PS_1C_CTRL 0x69180
> +#define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \
> + _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \
> + _ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
Side note: we should probably look doing something similar
to _SKL_PLANE()/etc. for this stuff. Perhaps that can b
e just renamed and reused for here (would actually
need to think for which it's too late right now)?
> #define PS_SCALER_EN REG_BIT(31)
> #define PS_SCALER_TYPE_MASK REG_BIT(30) /* icl+ */
> #define PS_SCALER_TYPE_NON_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 0)
> @@ -2286,6 +2290,9 @@
> #define _PS_PWR_GATE_1B 0x68960
> #define _PS_PWR_GATE_2B 0x68A60
> #define _PS_PWR_GATE_1C 0x69160
> +#define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \
> + _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
> + _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
> #define PS_PWR_GATE_DIS_OVERRIDE REG_BIT(31)
> #define PS_PWR_GATE_SETTLING_TIME_MASK REG_GENMASK(4, 3)
> #define PS_PWR_GATE_SETTLING_TIME_32 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 0)
> @@ -2303,6 +2310,9 @@
> #define _PS_WIN_POS_1B 0x68970
> #define _PS_WIN_POS_2B 0x68A70
> #define _PS_WIN_POS_1C 0x69170
> +#define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \
> + _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
> + _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
> #define PS_WIN_XPOS_MASK REG_GENMASK(31, 16)
> #define PS_WIN_XPOS(x) REG_FIELD_PREP(PS_WIN_XPOS_MASK, (x))
> #define PS_WIN_YPOS_MASK REG_GENMASK(15, 0)
> @@ -2313,6 +2323,9 @@
> #define _PS_WIN_SZ_1B 0x68974
> #define _PS_WIN_SZ_2B 0x68A74
> #define _PS_WIN_SZ_1C 0x69174
> +#define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \
> + _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \
> + _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
> #define PS_WIN_XSIZE_MASK REG_GENMASK(31, 16)
> #define PS_WIN_XSIZE(w) REG_FIELD_PREP(PS_WIN_XSIZE_MASK, (w))
> #define PS_WIN_YSIZE_MASK REG_GENMASK(15, 0)
> @@ -2323,18 +2336,27 @@
> #define _PS_VSCALE_1B 0x68984
> #define _PS_VSCALE_2B 0x68A84
> #define _PS_VSCALE_1C 0x69184
> +#define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \
> + _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \
> + _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
>
> #define _PS_HSCALE_1A 0x68190
> #define _PS_HSCALE_2A 0x68290
> #define _PS_HSCALE_1B 0x68990
> #define _PS_HSCALE_2B 0x68A90
> #define _PS_HSCALE_1C 0x69190
> +#define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \
> + _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \
> + _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
>
> #define _PS_VPHASE_1A 0x68188
> #define _PS_VPHASE_2A 0x68288
> #define _PS_VPHASE_1B 0x68988
> #define _PS_VPHASE_2B 0x68A88
> #define _PS_VPHASE_1C 0x69188
> +#define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \
> + _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \
> + _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
> #define PS_Y_PHASE_MASK REG_GENMASK(31, 16)
> #define PS_Y_PHASE(x) REG_FIELD_PREP(PS_Y_PHASE_MASK, (x))
> #define PS_UV_RGB_PHASE_MASK REG_GENMASK(15, 0)
> @@ -2347,56 +2369,32 @@
> #define _PS_HPHASE_1B 0x68994
> #define _PS_HPHASE_2B 0x68A94
> #define _PS_HPHASE_1C 0x69194
> +#define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \
> + _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \
> + _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
>
> #define _PS_ECC_STAT_1A 0x681D0
> #define _PS_ECC_STAT_2A 0x682D0
> #define _PS_ECC_STAT_1B 0x689D0
> #define _PS_ECC_STAT_2B 0x68AD0
> #define _PS_ECC_STAT_1C 0x691D0
> +#define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \
> + _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
> + _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
>
> #define _PS_COEF_SET0_INDEX_1A 0x68198
> #define _PS_COEF_SET0_INDEX_2A 0x68298
> #define _PS_COEF_SET0_INDEX_1B 0x68998
> #define _PS_COEF_SET0_INDEX_2B 0x68A98
> +#define GLK_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe, \
> + _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \
> + _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8)
> #define PS_COEF_INDEX_AUTO_INC REG_BIT(10)
>
> #define _PS_COEF_SET0_DATA_1A 0x6819C
> #define _PS_COEF_SET0_DATA_2A 0x6829C
> #define _PS_COEF_SET0_DATA_1B 0x6899C
> #define _PS_COEF_SET0_DATA_2B 0x68A9C
> -
> -#define _ID(id, a, b) _PICK_EVEN(id, a, b)
> -#define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \
> - _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \
> - _ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
> -#define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \
> - _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
> - _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
> -#define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \
> - _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
> - _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
> -#define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \
> - _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \
> - _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
> -#define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \
> - _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \
> - _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
> -#define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \
> - _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \
> - _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
> -#define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \
> - _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \
> - _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
> -#define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \
> - _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \
> - _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
> -#define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \
> - _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
> - _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
> -#define GLK_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe, \
> - _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \
> - _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8)
> -
> #define GLK_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \
> _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \
> _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8)
> --
> 2.39.2
--
Ville Syrjälä
Intel
next prev parent reply other threads:[~2024-09-09 21:01 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-09 18:58 [PATCH 00/11] drm/i915: split out display regs Jani Nikula
2024-09-09 18:58 ` [PATCH 01/11] drm/i915/reg: fix transcoder timing register style Jani Nikula
2024-09-09 18:58 ` [PATCH 02/11] drm/i915/reg: fix g4x pipe data/link m/n " Jani Nikula
2024-09-09 18:58 ` [PATCH 03/11] drm/i915/reg: fix pipe conf, stat etc. " Jani Nikula
2024-09-09 18:58 ` [PATCH 04/11] drm/i915/reg: fix pipe data/link m/n " Jani Nikula
2024-09-09 18:58 ` [PATCH 05/11] drm/i915/reg: fix SKL scaler " Jani Nikula
2024-09-09 21:01 ` Ville Syrjälä [this message]
2024-09-09 18:58 ` [PATCH 06/11] drm/i915/reg: fix PCH transcoder timing and data/link m/n style Jani Nikula
2024-09-09 21:01 ` Ville Syrjälä
2024-09-10 8:05 ` Jani Nikula
2024-09-10 11:48 ` Ville Syrjälä
2024-09-09 18:58 ` [PATCH 07/11] drm/i915/reg: fix DIP CTL register style Jani Nikula
2024-09-09 18:58 ` [PATCH 08/11] drm/i915/reg: fix small register style issues here and there Jani Nikula
2024-09-09 18:59 ` [PATCH 09/11] drm/i915/reg: remove unused DSI register macros Jani Nikula
2024-09-09 18:59 ` [PATCH 10/11] drm/i915/reg: remove superfluous whitespace Jani Nikula
2024-09-09 18:59 ` [PATCH 11/11] drm/i915: split out display regs from i915_reg.h Jani Nikula
2024-09-09 20:57 ` Ville Syrjälä
2024-09-09 21:18 ` Jani Nikula
2024-09-10 11:58 ` Ville Syrjälä
2024-09-09 19:37 ` ✓ CI.Patch_applied: success for drm/i915: split out display regs Patchwork
2024-09-09 19:38 ` ✗ CI.checkpatch: warning " Patchwork
2024-09-09 19:39 ` ✓ CI.KUnit: success " Patchwork
2024-09-09 19:51 ` ✓ CI.Build: " Patchwork
2024-09-09 19:53 ` ✓ CI.Hooks: " Patchwork
2024-09-09 19:55 ` ✗ CI.checksparse: warning " Patchwork
2024-09-09 20:09 ` ✓ CI.BAT: success " Patchwork
2024-09-09 21:03 ` [PATCH 00/11] " Ville Syrjälä
2024-09-10 13:32 ` Jani Nikula
2024-09-09 21:10 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2024-09-09 21:10 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-09-09 21:19 ` ✓ Fi.CI.BAT: success " Patchwork
2024-09-10 0:17 ` ✓ CI.FULL: " Patchwork
2024-09-10 23:20 ` ✗ Fi.CI.IGT: failure " Patchwork
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