All of lore.kernel.org
 help / color / mirror / Atom feed
From: Joerg Roedel <joro@8bytes.org>
To: Tomasz Jeznach <tjeznach@rivosinc.com>
Cc: Will Deacon <will@kernel.org>,
	Robin Murphy <robin.murphy@arm.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Anup Patel <apatel@ventanamicro.com>,
	Sunil V L <sunilvl@ventanamicro.com>,
	Nick Kossifidis <mick@ics.forth.gr>,
	Sebastien Boeuf <seb@rivosinc.com>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	devicetree@vger.kernel.org, iommu@lists.linux.dev,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	linux@rivosinc.com
Subject: Re: [PATCH v9 0/7] Linux RISC-V IOMMU Support
Date: Tue, 15 Oct 2024 10:50:36 +0200	[thread overview]
Message-ID: <Zw4s3BHQZ6x4d79-@8bytes.org> (raw)
In-Reply-To: <cover.1728579958.git.tjeznach@rivosinc.com>

On Thu, Oct 10, 2024 at 12:48:03PM -0700, Tomasz Jeznach wrote:
> This patch series introduces support for RISC-V IOMMU architected
> hardware into the Linux kernel.

Thanks Tomasz. I plan to merge this driver into the IOMMU tree if no
further objections are raised in this thread by Friday.

Regards,

	Joerg


WARNING: multiple messages have this Message-ID (diff)
From: Joerg Roedel <joro@8bytes.org>
To: Tomasz Jeznach <tjeznach@rivosinc.com>
Cc: Anup Patel <apatel@ventanamicro.com>,
	devicetree@vger.kernel.org, Conor Dooley <conor+dt@kernel.org>,
	Albert Ou <aou@eecs.berkeley.edu>,
	linux@rivosinc.com, Will Deacon <will@kernel.org>,
	linux-kernel@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
	Sebastien Boeuf <seb@rivosinc.com>,
	iommu@lists.linux.dev, Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Nick Kossifidis <mick@ics.forth.gr>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Robin Murphy <robin.murphy@arm.com>,
	linux-riscv@lists.infradead.org
Subject: Re: [PATCH v9 0/7] Linux RISC-V IOMMU Support
Date: Tue, 15 Oct 2024 10:50:36 +0200	[thread overview]
Message-ID: <Zw4s3BHQZ6x4d79-@8bytes.org> (raw)
In-Reply-To: <cover.1728579958.git.tjeznach@rivosinc.com>

On Thu, Oct 10, 2024 at 12:48:03PM -0700, Tomasz Jeznach wrote:
> This patch series introduces support for RISC-V IOMMU architected
> hardware into the Linux kernel.

Thanks Tomasz. I plan to merge this driver into the IOMMU tree if no
further objections are raised in this thread by Friday.

Regards,

	Joerg


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  parent reply	other threads:[~2024-10-15  8:50 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-10 19:48 [PATCH v9 0/7] Linux RISC-V IOMMU Support Tomasz Jeznach
2024-10-10 19:48 ` Tomasz Jeznach
2024-10-10 19:48 ` [PATCH v9 1/7] dt-bindings: iommu: riscv: Add bindings for RISC-V IOMMU Tomasz Jeznach
2024-10-10 19:48   ` Tomasz Jeznach
2024-10-10 19:48 ` [PATCH v9 2/7] iommu/riscv: Add RISC-V IOMMU platform device driver Tomasz Jeznach
2024-10-10 19:48   ` Tomasz Jeznach
2024-10-15  8:50   ` Will Deacon
2024-10-15  8:50     ` Will Deacon
2024-10-16  6:46     ` Tomasz Jeznach
2024-10-16  6:46       ` Tomasz Jeznach
2024-10-16  9:35   ` Uwe Kleine-König
2024-10-16  9:35     ` Uwe Kleine-König
2024-10-17 16:45     ` Tomasz Jeznach
2024-10-17 16:45       ` Tomasz Jeznach
2024-10-18  5:31       ` Uwe Kleine-König
2024-10-18  5:31         ` Uwe Kleine-König
2024-10-10 19:48 ` [PATCH v9 3/7] iommu/riscv: Add RISC-V IOMMU PCIe " Tomasz Jeznach
2024-10-10 19:48   ` Tomasz Jeznach
2024-10-10 19:48 ` [PATCH v9 4/7] iommu/riscv: Enable IOMMU registration and device probe Tomasz Jeznach
2024-10-10 19:48   ` Tomasz Jeznach
2024-10-10 19:48 ` [PATCH v9 5/7] iommu/riscv: Device directory management Tomasz Jeznach
2024-10-10 19:48   ` Tomasz Jeznach
2024-10-10 19:48 ` [PATCH v9 6/7] iommu/riscv: Command and fault queue support Tomasz Jeznach
2024-10-10 19:48   ` Tomasz Jeznach
2024-10-15  8:58   ` Will Deacon
2024-10-15  8:58     ` Will Deacon
2024-10-16  6:49     ` Tomasz Jeznach
2024-10-16  6:49       ` Tomasz Jeznach
2024-10-10 19:48 ` [PATCH v9 7/7] iommu/riscv: Paging domain support Tomasz Jeznach
2024-10-10 19:48   ` Tomasz Jeznach
2024-10-15 16:20   ` Jason Gunthorpe
2024-10-15 16:20     ` Jason Gunthorpe
2024-10-15  8:50 ` Joerg Roedel [this message]
2024-10-15  8:50   ` [PATCH v9 0/7] Linux RISC-V IOMMU Support Joerg Roedel
2024-10-15  8:59   ` Will Deacon
2024-10-15  8:59     ` Will Deacon
2024-10-16  6:58     ` Tomasz Jeznach
2024-10-16  6:58       ` Tomasz Jeznach

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=Zw4s3BHQZ6x4d79-@8bytes.org \
    --to=joro@8bytes.org \
    --cc=aou@eecs.berkeley.edu \
    --cc=apatel@ventanamicro.com \
    --cc=conor+dt@kernel.org \
    --cc=devicetree@vger.kernel.org \
    --cc=iommu@lists.linux.dev \
    --cc=krzk+dt@kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=linux@rivosinc.com \
    --cc=mick@ics.forth.gr \
    --cc=palmer@dabbelt.com \
    --cc=paul.walmsley@sifive.com \
    --cc=robh+dt@kernel.org \
    --cc=robin.murphy@arm.com \
    --cc=seb@rivosinc.com \
    --cc=sunilvl@ventanamicro.com \
    --cc=tjeznach@rivosinc.com \
    --cc=will@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.