From: Vinod Koul <vkoul@kernel.org>
To: Bartosz Wawrzyniak <bwawrzyn@cisco.com>
Cc: Kishon Vijay Abraham I <kishon@kernel.org>,
Christophe JAILLET <christophe.jaillet@wanadoo.fr>,
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
Aswath Govindraju <a-govindraju@ti.com>,
Swapnil Jakhade <sjakhade@cadence.com>,
linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org,
xe-linux-external@cisco.com, Daniel Walker <danielwa@cisco.com>,
Bartosz Stania <sbartosz@cisco.com>
Subject: Re: [PATCH] phy: cadence: Sierra: Fix offset of DEQ open eye algorithm control register
Date: Mon, 7 Oct 2024 11:55:55 +0530 [thread overview]
Message-ID: <ZwN+8xpOl4+Ggaha@vaman> (raw)
In-Reply-To: <20241003123405.1101157-1-bwawrzyn@cisco.com>
On 03-10-24, 12:34, Bartosz Wawrzyniak wrote:
> Fix the value of SIERRA_DEQ_OPENEYE_CTRL_PREG and add a definition for
> SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG. This fixes the SGMII single link
> register configuration.
>
> Fixes: 7a5ad9b4b98c ("phy: cadence: Sierra: Update single link PCIe register configuration")
>
No need for this empty line here
> Signed-off-by: Bartosz Wawrzyniak <bwawrzyn@cisco.com>
--
~Vinod
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
WARNING: multiple messages have this Message-ID (diff)
From: Vinod Koul <vkoul@kernel.org>
To: Bartosz Wawrzyniak <bwawrzyn@cisco.com>
Cc: Kishon Vijay Abraham I <kishon@kernel.org>,
Christophe JAILLET <christophe.jaillet@wanadoo.fr>,
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
Aswath Govindraju <a-govindraju@ti.com>,
Swapnil Jakhade <sjakhade@cadence.com>,
linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org,
xe-linux-external@cisco.com, Daniel Walker <danielwa@cisco.com>,
Bartosz Stania <sbartosz@cisco.com>
Subject: Re: [PATCH] phy: cadence: Sierra: Fix offset of DEQ open eye algorithm control register
Date: Mon, 7 Oct 2024 11:55:55 +0530 [thread overview]
Message-ID: <ZwN+8xpOl4+Ggaha@vaman> (raw)
In-Reply-To: <20241003123405.1101157-1-bwawrzyn@cisco.com>
On 03-10-24, 12:34, Bartosz Wawrzyniak wrote:
> Fix the value of SIERRA_DEQ_OPENEYE_CTRL_PREG and add a definition for
> SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG. This fixes the SGMII single link
> register configuration.
>
> Fixes: 7a5ad9b4b98c ("phy: cadence: Sierra: Update single link PCIe register configuration")
>
No need for this empty line here
> Signed-off-by: Bartosz Wawrzyniak <bwawrzyn@cisco.com>
--
~Vinod
next prev parent reply other threads:[~2024-10-07 6:32 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-03 12:34 [PATCH] phy: cadence: Sierra: Fix offset of DEQ open eye algorithm control register Bartosz Wawrzyniak
2024-10-03 12:34 ` Bartosz Wawrzyniak
2024-10-07 6:25 ` Vinod Koul [this message]
2024-10-07 6:25 ` Vinod Koul
2024-10-08 17:09 ` [PATCH v2] " Bartosz Wawrzyniak
2024-10-08 17:09 ` Bartosz Wawrzyniak
2024-10-17 14:58 ` Vinod Koul
2024-10-17 14:58 ` Vinod Koul
2024-10-18 10:40 ` Bartosz Wawrzyniak -X (bwawrzyn - GLOBALLOGIC INC at Cisco)
2024-10-18 10:40 ` Bartosz Wawrzyniak -X (bwawrzyn - GLOBALLOGIC INC at Cisco)
2024-10-07 15:49 ` [PATCH] " Vinod Koul
2024-10-07 15:49 ` Vinod Koul
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