Re: [PATCH v2 5/7] i386/cpu: Support thread and module level cache topology

[Zhao Liu <zhao1.liu@intel.com>]

On Tue, Sep 17, 2024 at 10:05:08AM +0100, Jonathan Cameron wrote:
> Date: Tue, 17 Sep 2024 10:05:08 +0100
> From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
> Subject: Re: [PATCH v2 5/7] i386/cpu: Support thread and module level cache
>  topology
> X-Mailer: Claws Mail 4.1.0 (GTK 3.24.33; x86_64-w64-mingw32)
> 
> On Sun,  8 Sep 2024 20:59:18 +0800
> Zhao Liu <zhao1.liu@intel.com> wrote:
> 
> > Allow cache to be defined at the thread and module level. This
> > increases flexibility for x86 users to customize their cache topology.
> > 
> > Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
> > Tested-by: Yongwei Ma <yongwei.ma@intel.com>
>
> Will be interesting to see if anyone uses the thread level, but
> no harm in supporting it.

x86 CPU has a legacy property "x-l1-cache-per-thread". This is the old
QEMU cache topology behavior, kept for compatibility. Now add thread
level and I can refactor the code for this thread level.

> I guess this would be a case of RDT
> / MPAM etc as I'm not sure I've seen an SMT processor with
> private caches. Some old papers seems to suggest that it might
> make sense for smt 8 and above.

Thanks for the hint, I'll think about whether some of the RDT / MPAM
cases can be applied here.

> Anyhow, patch is fine
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

Thanks!

-Zhao