From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Tyrone Ting <warp5tw@gmail.com>
Cc: avifishman70@gmail.com, tmaimon77@gmail.com,
tali.perry1@gmail.com, venture@google.com, yuenn@google.com,
benjaminfair@google.com, andi.shyti@kernel.org, wsa@kernel.org,
rand.sec96@gmail.com, wsa+renesas@sang-engineering.com,
tali.perry@nuvoton.com, Avi.Fishman@nuvoton.com,
tomer.maimon@nuvoton.com, KWLIU@nuvoton.com, JJLIU0@nuvoton.com,
kfting@nuvoton.com, openbmc@lists.ozlabs.org,
linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v5 4/6] i2c: npcm: Modify the client address assignment
Date: Tue, 8 Oct 2024 19:21:46 +0300 [thread overview]
Message-ID: <ZwVcGu3YeJ6pI0sM@black.fi.intel.com> (raw)
In-Reply-To: <CACD3sJa23TEfBQ_b8PGM8ot2L0g4n=GcqvPk0HJGjRf-d+=-pg@mail.gmail.com>
On Fri, Oct 04, 2024 at 10:29:10AM +0800, Tyrone Ting wrote:
> Hi Andy:
>
> Thank you for your comments.
>
> After a second thought, I'll explain why slave_addr << 1 is given here.
>
> Tyrone Ting <warp5tw@gmail.com> 於 2024年10月4日 週五 上午9:49寫道:
> >
> > Hi Andy:
> >
> > Thank you for your comments and they'll be addressed.
> >
> > Andy Shevchenko <andriy.shevchenko@linux.intel.com> 於 2024年10月1日 週二 下午9:17寫道:
> > >
> > > On Tue, Oct 01, 2024 at 02:28:53PM +0800, Tyrone Ting wrote:
> > > > From: Tyrone Ting <kfting@nuvoton.com>
> > > >
> > > > Store the client address earlier since it might get called in
> > > > the i2c_recover_bus() logic flow at the early stage of
> > > > npcm_i2c_master_xfer().
> > >
> > > ...
> > >
> > > > + /*
> > > > + * Previously, the address was stored w/o left-shift by one bit and
> > > > + * with that shift in the following call to npcm_i2c_master_start_xmit().
> > > > + *
> > > > + * Since there are cases that the i2c_recover_bus() gets called at the
> > > > + * early stage of npcm_i2c_master_xfer(), the address is stored with
> > > > + * the shift and used in the i2c_recover_bus().
> > > > + *
> > > > + * The address is stored from bit 1 to bit 7 in the register for
> > > > + * sending the i2c address later so it's left-shifted by 1 bit.
> > > > + */
> > > > + bus->dest_addr = slave_addr << 1;
> > >
> > > I'm wondering if it's better to use i2c_8bit_addr_from_msg() here?
> > >
>
> The current implementation of i2c_8bit_addr_from_msg() (ref link:
> https://github.com/torvalds/linux/blob/master/include/linux/i2c.h#L947)
> is
> "return (msg->addr << 1) | (msg->flags & I2C_M_RD);" and it takes
> extra consideration about the read flag when retrieving the i2c
> address.
> IOW, if there is a read event, the i2c address contains a read
> indication (bit 0 of the i2c address is 1).
>
> The patch code "bus->dest_addr = slave_addr << 1;" might get used in
> i2c_recover_bus() later. (ref link:
> https://github.com/torvalds/linux/blob/master/drivers/i2c/busses/i2c-npcm7xx.c#L1691)
>
> Suppose there is a read event and the i2c address is 0x60.
>
> With i2c_8bit_addr_from_msg(), bus->dest_addr will be 0xc1.
> With the original patch, bus->dest_addr will be 0xc0.
>
> If some error condition occurs and it requires i2c_recover_bus() to
> recover the bus, according to the description at
> https://github.com/torvalds/linux/blob/master/drivers/i2c/busses/i2c-npcm7xx.c#L1742,
> the address "0xc1" is used
> as a parameter to npcm_i2c_wr_byte() which is used to send the address
> in the write direction.
>
> If i2c_8bit_addr_from_msg() is applied, it might not fit the scenario
> described at
> https://github.com/torvalds/linux/blob/master/drivers/i2c/busses/i2c-npcm7xx.c#L1742,
> which is about to send
> an address in a write direction since the address from
> i2c_8bit_addr_from_msg() contains a read indication.
Okay, then I would do the i2c_8bit_addr_from_msg() call here as AFAICS
this is the real event where you save the address *of the event*.
And in the respective user update the comment to summarize above and do
rather ->dest_addr & ~I2C_M_RD there.
--
With Best Regards,
Andy Shevchenko
WARNING: multiple messages have this Message-ID (diff)
From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Tyrone Ting <warp5tw@gmail.com>
Cc: KWLIU@nuvoton.com, tomer.maimon@nuvoton.com,
linux-kernel@vger.kernel.org, benjaminfair@google.com,
wsa+renesas@sang-engineering.com, avifishman70@gmail.com,
venture@google.com, openbmc@lists.ozlabs.org, kfting@nuvoton.com,
JJLIU0@nuvoton.com, tali.perry@nuvoton.com,
tali.perry1@gmail.com, wsa@kernel.org, andi.shyti@kernel.org,
linux-i2c@vger.kernel.org, Avi.Fishman@nuvoton.com,
rand.sec96@gmail.com, tmaimon77@gmail.com
Subject: Re: [PATCH v5 4/6] i2c: npcm: Modify the client address assignment
Date: Tue, 8 Oct 2024 19:21:46 +0300 [thread overview]
Message-ID: <ZwVcGu3YeJ6pI0sM@black.fi.intel.com> (raw)
In-Reply-To: <CACD3sJa23TEfBQ_b8PGM8ot2L0g4n=GcqvPk0HJGjRf-d+=-pg@mail.gmail.com>
On Fri, Oct 04, 2024 at 10:29:10AM +0800, Tyrone Ting wrote:
> Hi Andy:
>
> Thank you for your comments.
>
> After a second thought, I'll explain why slave_addr << 1 is given here.
>
> Tyrone Ting <warp5tw@gmail.com> 於 2024年10月4日 週五 上午9:49寫道:
> >
> > Hi Andy:
> >
> > Thank you for your comments and they'll be addressed.
> >
> > Andy Shevchenko <andriy.shevchenko@linux.intel.com> 於 2024年10月1日 週二 下午9:17寫道:
> > >
> > > On Tue, Oct 01, 2024 at 02:28:53PM +0800, Tyrone Ting wrote:
> > > > From: Tyrone Ting <kfting@nuvoton.com>
> > > >
> > > > Store the client address earlier since it might get called in
> > > > the i2c_recover_bus() logic flow at the early stage of
> > > > npcm_i2c_master_xfer().
> > >
> > > ...
> > >
> > > > + /*
> > > > + * Previously, the address was stored w/o left-shift by one bit and
> > > > + * with that shift in the following call to npcm_i2c_master_start_xmit().
> > > > + *
> > > > + * Since there are cases that the i2c_recover_bus() gets called at the
> > > > + * early stage of npcm_i2c_master_xfer(), the address is stored with
> > > > + * the shift and used in the i2c_recover_bus().
> > > > + *
> > > > + * The address is stored from bit 1 to bit 7 in the register for
> > > > + * sending the i2c address later so it's left-shifted by 1 bit.
> > > > + */
> > > > + bus->dest_addr = slave_addr << 1;
> > >
> > > I'm wondering if it's better to use i2c_8bit_addr_from_msg() here?
> > >
>
> The current implementation of i2c_8bit_addr_from_msg() (ref link:
> https://github.com/torvalds/linux/blob/master/include/linux/i2c.h#L947)
> is
> "return (msg->addr << 1) | (msg->flags & I2C_M_RD);" and it takes
> extra consideration about the read flag when retrieving the i2c
> address.
> IOW, if there is a read event, the i2c address contains a read
> indication (bit 0 of the i2c address is 1).
>
> The patch code "bus->dest_addr = slave_addr << 1;" might get used in
> i2c_recover_bus() later. (ref link:
> https://github.com/torvalds/linux/blob/master/drivers/i2c/busses/i2c-npcm7xx.c#L1691)
>
> Suppose there is a read event and the i2c address is 0x60.
>
> With i2c_8bit_addr_from_msg(), bus->dest_addr will be 0xc1.
> With the original patch, bus->dest_addr will be 0xc0.
>
> If some error condition occurs and it requires i2c_recover_bus() to
> recover the bus, according to the description at
> https://github.com/torvalds/linux/blob/master/drivers/i2c/busses/i2c-npcm7xx.c#L1742,
> the address "0xc1" is used
> as a parameter to npcm_i2c_wr_byte() which is used to send the address
> in the write direction.
>
> If i2c_8bit_addr_from_msg() is applied, it might not fit the scenario
> described at
> https://github.com/torvalds/linux/blob/master/drivers/i2c/busses/i2c-npcm7xx.c#L1742,
> which is about to send
> an address in a write direction since the address from
> i2c_8bit_addr_from_msg() contains a read indication.
Okay, then I would do the i2c_8bit_addr_from_msg() call here as AFAICS
this is the real event where you save the address *of the event*.
And in the respective user update the comment to summarize above and do
rather ->dest_addr & ~I2C_M_RD there.
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2024-10-08 16:21 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-01 6:28 [PATCH v5 0/6] i2c: npcm: read/write operation, checkpatch Tyrone Ting
2024-10-01 6:28 ` [PATCH v5 1/6] i2c: npcm: correct the read/write operation procedure Tyrone Ting
2024-10-01 6:28 ` [PATCH v5 2/6] i2c: npcm: use a software flag to indicate a BER condition Tyrone Ting
2024-10-01 6:28 ` [PATCH v5 3/6] i2c: npcm: Modify timeout evaluation mechanism Tyrone Ting
2024-10-01 13:14 ` Andy Shevchenko
2024-10-01 13:14 ` Andy Shevchenko
2024-10-09 5:49 ` Tyrone Ting
2024-10-09 5:49 ` Tyrone Ting
2024-10-01 6:28 ` [PATCH v5 4/6] i2c: npcm: Modify the client address assignment Tyrone Ting
2024-10-01 13:17 ` Andy Shevchenko
2024-10-01 13:17 ` Andy Shevchenko
2024-10-04 1:49 ` Tyrone Ting
2024-10-04 1:49 ` Tyrone Ting
2024-10-04 2:29 ` Tyrone Ting
2024-10-04 2:29 ` Tyrone Ting
2024-10-08 1:41 ` Tyrone Ting
2024-10-08 1:41 ` Tyrone Ting
2024-10-08 16:21 ` Andy Shevchenko [this message]
2024-10-08 16:21 ` Andy Shevchenko
2024-10-09 5:48 ` Tyrone Ting
2024-10-09 5:48 ` Tyrone Ting
2024-10-01 6:28 ` [PATCH v5 5/6] i2c: npcm: use i2c frequency table Tyrone Ting
2024-10-01 13:23 ` Andy Shevchenko
2024-10-01 13:23 ` Andy Shevchenko
2024-10-04 1:51 ` Tyrone Ting
2024-10-04 1:51 ` Tyrone Ting
2024-10-01 6:28 ` [PATCH v5 6/6] i2c: npcm: Enable slave in eob interrupt Tyrone Ting
2024-10-01 6:28 ` Tyrone Ting
2024-10-02 8:34 ` [PATCH v5 0/6] i2c: npcm: read/write operation, checkpatch Andi Shyti
2024-10-02 8:34 ` Andi Shyti
2024-10-04 1:44 ` Tyrone Ting
2024-10-04 1:44 ` Tyrone Ting
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