From: Vinod Koul <vkoul@kernel.org>
To: Richard Zhu <hongxing.zhu@nxp.com>
Cc: kishon@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
festevam@gmail.com, Frank.Li@nxp.com,
marcel.ziswiler@toradex.com, linux-phy@lists.infradead.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev,
kernel@pengutronix.de, stable@vger.kernel.org
Subject: Re: [PATCH] phy: freescale: imx8m-pcie: Do CMN_RST just before PHY PLL lock check
Date: Thu, 17 Oct 2024 20:34:55 +0530 [thread overview]
Message-ID: <ZxEnlx8n4rojC779@vaman> (raw)
In-Reply-To: <1728444303-32416-1-git-send-email-hongxing.zhu@nxp.com>
On 09-10-24, 11:25, Richard Zhu wrote:
> When enable initcall_debug together with higher debug level below.
> CONFIG_CONSOLE_LOGLEVEL_DEFAULT=9
> CONFIG_CONSOLE_LOGLEVEL_QUIET=9
> CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
>
> The initialization of i.MX8MP PCIe PHY might be timeout failed randomly.
> To fix this issue, adjust the sequence of the resets refer to the power
> up sequence listed below.
This fails to apply on the phy/fixes, can you please rebase and send
--
~Vinod
WARNING: multiple messages have this Message-ID (diff)
From: Vinod Koul <vkoul@kernel.org>
To: Richard Zhu <hongxing.zhu@nxp.com>
Cc: kishon@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
festevam@gmail.com, Frank.Li@nxp.com,
marcel.ziswiler@toradex.com, linux-phy@lists.infradead.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev,
kernel@pengutronix.de, stable@vger.kernel.org
Subject: Re: [PATCH] phy: freescale: imx8m-pcie: Do CMN_RST just before PHY PLL lock check
Date: Thu, 17 Oct 2024 20:34:55 +0530 [thread overview]
Message-ID: <ZxEnlx8n4rojC779@vaman> (raw)
In-Reply-To: <1728444303-32416-1-git-send-email-hongxing.zhu@nxp.com>
On 09-10-24, 11:25, Richard Zhu wrote:
> When enable initcall_debug together with higher debug level below.
> CONFIG_CONSOLE_LOGLEVEL_DEFAULT=9
> CONFIG_CONSOLE_LOGLEVEL_QUIET=9
> CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
>
> The initialization of i.MX8MP PCIe PHY might be timeout failed randomly.
> To fix this issue, adjust the sequence of the resets refer to the power
> up sequence listed below.
This fails to apply on the phy/fixes, can you please rebase and send
--
~Vinod
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
next prev parent reply other threads:[~2024-10-17 15:04 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-09 3:25 [PATCH] phy: freescale: imx8m-pcie: Do CMN_RST just before PHY PLL lock check Richard Zhu
2024-10-09 3:25 ` Richard Zhu
2024-10-17 15:04 ` Vinod Koul [this message]
2024-10-17 15:04 ` Vinod Koul
2024-10-22 5:31 ` Vinod Koul
2024-10-22 5:31 ` Vinod Koul
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