[PATCH 0/4] cpufreq/amd-pstate:Cleanups

[PATCH 0/4] cpufreq/amd-pstate:Cleanups

[Dhananjay Ugwekar]

Explicitly rename functions that enable CPPC as *_cppc_*. 

Do not clear MSR_AMD_CPPC_ENABLE as it is a set-once register, i.e. it 
cannot be cleared. 

Propagate the epp value to shared mem in the reenable function.

Replicate the offline flow of MSR based systems in shared mem systems.

Dhananjay Ugwekar (4):
  cpufreq/amd-pstate: Rename functions that enable CPPC
  cpufreq/amd-pstate: Do not attempt to clear MSR_AMD_CPPC_ENABLE
  cpufreq/amd-pstate: Call cppc_set_epp_perf in the reenable function
  cpufreq/amd-pstate: Align offline flow of shared memory and MSR based
    systems

 drivers/cpufreq/amd-pstate.c | 39 ++++++++++++++++++++++--------------
 1 file changed, 24 insertions(+), 15 deletions(-)

-- 
2.34.1

[PATCH 1/4] cpufreq/amd-pstate: Rename functions that enable CPPC

[Dhananjay Ugwekar]

Explicitly rename functions that enable CPPC as *_cppc_*.

Signed-off-by: Dhananjay Ugwekar <Dhananjay.Ugwekar@amd.com>
---
 drivers/cpufreq/amd-pstate.c | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
index 3c14962adeb2..0b4a4d69c14d 100644
--- a/drivers/cpufreq/amd-pstate.c
+++ b/drivers/cpufreq/amd-pstate.c
@@ -306,7 +306,7 @@ static int amd_pstate_set_energy_pref_index(struct amd_cpudata *cpudata,
 	return ret;
 }
 
-static inline int msr_enable(bool enable)
+static inline int msr_cppc_enable(bool enable)
 {
 	int ret, cpu;
 	unsigned long logical_proc_id_mask = 0;
@@ -332,7 +332,7 @@ static inline int msr_enable(bool enable)
 	return 0;
 }
 
-static int shmem_enable(bool enable)
+static int shmem_cppc_enable(bool enable)
 {
 	int cpu, ret = 0;
 	struct cppc_perf_ctrls perf_ctrls;
@@ -359,11 +359,11 @@ static int shmem_enable(bool enable)
 	return ret;
 }
 
-DEFINE_STATIC_CALL(amd_pstate_enable, msr_enable);
+DEFINE_STATIC_CALL(amd_pstate_cppc_enable, msr_cppc_enable);
 
-static inline int amd_pstate_enable(bool enable)
+static inline int amd_pstate_cppc_enable(bool enable)
 {
-	return static_call(amd_pstate_enable)(enable);
+	return static_call(amd_pstate_cppc_enable)(enable);
 }
 
 static int msr_init_perf(struct amd_cpudata *cpudata)
@@ -1042,7 +1042,7 @@ static int amd_pstate_cpu_resume(struct cpufreq_policy *policy)
 {
 	int ret;
 
-	ret = amd_pstate_enable(true);
+	ret = amd_pstate_cppc_enable(true);
 	if (ret)
 		pr_err("failed to enable amd-pstate during resume, return %d\n", ret);
 
@@ -1053,7 +1053,7 @@ static int amd_pstate_cpu_suspend(struct cpufreq_policy *policy)
 {
 	int ret;
 
-	ret = amd_pstate_enable(false);
+	ret = amd_pstate_cppc_enable(false);
 	if (ret)
 		pr_err("failed to disable amd-pstate during suspend, return %d\n", ret);
 
@@ -1186,7 +1186,7 @@ static ssize_t show_energy_performance_preference(
 
 static void amd_pstate_driver_cleanup(void)
 {
-	amd_pstate_enable(false);
+	amd_pstate_cppc_enable(false);
 	cppc_state = AMD_PSTATE_DISABLE;
 	current_pstate_driver = NULL;
 }
@@ -1220,7 +1220,7 @@ static int amd_pstate_register_driver(int mode)
 
 	cppc_state = mode;
 
-	ret = amd_pstate_enable(true);
+	ret = amd_pstate_cppc_enable(true);
 	if (ret) {
 		pr_err("failed to enable cppc during amd-pstate driver registration, return %d\n",
 		       ret);
@@ -1599,7 +1599,7 @@ static void amd_pstate_epp_reenable(struct amd_cpudata *cpudata)
 	u64 value, max_perf;
 	int ret;
 
-	ret = amd_pstate_enable(true);
+	ret = amd_pstate_cppc_enable(true);
 	if (ret)
 		pr_err("failed to enable amd pstate during resume, return %d\n", ret);
 
@@ -1686,7 +1686,7 @@ static int amd_pstate_epp_suspend(struct cpufreq_policy *policy)
 	cpudata->suspended = true;
 
 	/* disable CPPC in lowlevel firmware */
-	ret = amd_pstate_enable(false);
+	ret = amd_pstate_cppc_enable(false);
 	if (ret)
 		pr_err("failed to suspend, return %d\n", ret);
 
@@ -1861,7 +1861,7 @@ static int __init amd_pstate_init(void)
 			current_pstate_driver->adjust_perf = amd_pstate_adjust_perf;
 	} else {
 		pr_debug("AMD CPPC shared memory based functionality is supported\n");
-		static_call_update(amd_pstate_enable, shmem_enable);
+		static_call_update(amd_pstate_cppc_enable, shmem_cppc_enable);
 		static_call_update(amd_pstate_init_perf, shmem_init_perf);
 		static_call_update(amd_pstate_update_perf, shmem_update_perf);
 	}
@@ -1886,7 +1886,7 @@ static int __init amd_pstate_init(void)
 
 global_attr_free:
 	cpufreq_unregister_driver(current_pstate_driver);
-	amd_pstate_enable(false);
+	amd_pstate_cppc_enable(false);
 	return ret;
 }
 device_initcall(amd_pstate_init);
-- 
2.34.1

[PATCH 2/4] cpufreq/amd-pstate: Do not attempt to clear MSR_AMD_CPPC_ENABLE

[Dhananjay Ugwekar]

MSR_AMD_CPPC_ENABLE is a write once register, i.e. attempting to clear
it is futile, it will not take effect. Hence, return if disable (0)
argument is passed to the msr_cppc_enable()

Signed-off-by: Dhananjay Ugwekar <Dhananjay.Ugwekar@amd.com>
---
 drivers/cpufreq/amd-pstate.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
index 0b4a4d69c14d..576251e61ce0 100644
--- a/drivers/cpufreq/amd-pstate.c
+++ b/drivers/cpufreq/amd-pstate.c
@@ -311,6 +311,12 @@ static inline int msr_cppc_enable(bool enable)
 	int ret, cpu;
 	unsigned long logical_proc_id_mask = 0;
 
+       /*
+        * MSR_AMD_CPPC_ENABLE is write-once, once set it cannot be cleared.
+        */
+	if (!enable)
+		return 0;
+
 	if (enable == cppc_enabled)
 		return 0;
 
-- 
2.34.1

[PATCH 3/4] cpufreq/amd-pstate: Call cppc_set_epp_perf in the reenable function

[Dhananjay Ugwekar]

The EPP value being set in perf_ctrls.energy_perf is not being propagated
to the shared memory, fix that.

Signed-off-by: Dhananjay Ugwekar <Dhananjay.Ugwekar@amd.com>
---
 drivers/cpufreq/amd-pstate.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
index 576251e61ce0..bbeddce90823 100644
--- a/drivers/cpufreq/amd-pstate.c
+++ b/drivers/cpufreq/amd-pstate.c
@@ -1616,8 +1616,9 @@ static void amd_pstate_epp_reenable(struct amd_cpudata *cpudata)
 		wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
 	} else {
 		perf_ctrls.max_perf = max_perf;
-		perf_ctrls.energy_perf = AMD_CPPC_ENERGY_PERF_PREF(cpudata->epp_cached);
 		cppc_set_perf(cpudata->cpu, &perf_ctrls);
+		perf_ctrls.energy_perf = AMD_CPPC_ENERGY_PERF_PREF(cpudata->epp_cached);
+		cppc_set_epp_perf(cpudata->cpu, &perf_ctrls, 1);
 	}
 }
 
@@ -1658,8 +1659,9 @@ static void amd_pstate_epp_offline(struct cpufreq_policy *policy)
 	} else {
 		perf_ctrls.desired_perf = 0;
 		perf_ctrls.max_perf = min_perf;
-		perf_ctrls.energy_perf = AMD_CPPC_ENERGY_PERF_PREF(HWP_EPP_BALANCE_POWERSAVE);
 		cppc_set_perf(cpudata->cpu, &perf_ctrls);
+		perf_ctrls.energy_perf = AMD_CPPC_ENERGY_PERF_PREF(HWP_EPP_BALANCE_POWERSAVE);
+		cppc_set_epp_perf(cpudata->cpu, &perf_ctrls, 1);
 	}
 	mutex_unlock(&amd_pstate_limits_lock);
 }
-- 
2.34.1

[PATCH 4/4] cpufreq/amd-pstate: Align offline flow of shared memory and MSR based systems

[Dhananjay Ugwekar]

Set min_perf to lowest_perf for shared memory systems, similar to the MSR
based systems.

Signed-off-by: Dhananjay Ugwekar <Dhananjay.Ugwekar@amd.com>
---
 drivers/cpufreq/amd-pstate.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
index bbeddce90823..206725219d8c 100644
--- a/drivers/cpufreq/amd-pstate.c
+++ b/drivers/cpufreq/amd-pstate.c
@@ -1658,6 +1658,7 @@ static void amd_pstate_epp_offline(struct cpufreq_policy *policy)
 		wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
 	} else {
 		perf_ctrls.desired_perf = 0;
+		perf_ctrls.min_perf = min_perf;
 		perf_ctrls.max_perf = min_perf;
 		cppc_set_perf(cpudata->cpu, &perf_ctrls);
 		perf_ctrls.energy_perf = AMD_CPPC_ENERGY_PERF_PREF(HWP_EPP_BALANCE_POWERSAVE);
-- 
2.34.1

Re: [PATCH 0/4] cpufreq/amd-pstate:Cleanups

[Mario Limonciello]

On 10/23/2024 05:21, Dhananjay Ugwekar wrote:
> Explicitly rename functions that enable CPPC as *_cppc_*.
> 
> Do not clear MSR_AMD_CPPC_ENABLE as it is a set-once register, i.e. it
> cannot be cleared.
> 
> Propagate the epp value to shared mem in the reenable function.
> 
> Replicate the offline flow of MSR based systems in shared mem systems.
> 
> Dhananjay Ugwekar (4):
>    cpufreq/amd-pstate: Rename functions that enable CPPC
>    cpufreq/amd-pstate: Do not attempt to clear MSR_AMD_CPPC_ENABLE
>    cpufreq/amd-pstate: Call cppc_set_epp_perf in the reenable function
>    cpufreq/amd-pstate: Align offline flow of shared memory and MSR based
>      systems
> 
>   drivers/cpufreq/amd-pstate.c | 39 ++++++++++++++++++++++--------------
>   1 file changed, 24 insertions(+), 15 deletions(-)
> 

Thanks!

Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>

RE: [PATCH 1/4] cpufreq/amd-pstate: Rename functions that enable CPPC

[Yuan, Perry]

[AMD Official Use Only - AMD Internal Distribution Only]

> -----Original Message-----
> From: Ugwekar, Dhananjay <Dhananjay.Ugwekar@amd.com>
> Sent: Wednesday, October 23, 2024 6:21 PM
> To: Shenoy, Gautham Ranjal <gautham.shenoy@amd.com>; Limonciello, Mario
> <Mario.Limonciello@amd.com>; Yuan, Perry <Perry.Yuan@amd.com>;
> rafael@kernel.org; viresh.kumar@linaro.org
> Cc: linux-pm@vger.kernel.org; linux-kernel@vger.kernel.org; Ugwekar, Dhananjay
> <Dhananjay.Ugwekar@amd.com>
> Subject: [PATCH 1/4] cpufreq/amd-pstate: Rename functions that enable CPPC
>
> Explicitly rename functions that enable CPPC as *_cppc_*.
>
> Signed-off-by: Dhananjay Ugwekar <Dhananjay.Ugwekar@amd.com>
> ---
>  drivers/cpufreq/amd-pstate.c | 26 +++++++++++++-------------
>  1 file changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index
> 3c14962adeb2..0b4a4d69c14d 100644
> --- a/drivers/cpufreq/amd-pstate.c
> +++ b/drivers/cpufreq/amd-pstate.c
> @@ -306,7 +306,7 @@ static int amd_pstate_set_energy_pref_index(struct
> amd_cpudata *cpudata,
>       return ret;
>  }
>
> -static inline int msr_enable(bool enable)
> +static inline int msr_cppc_enable(bool enable)
>  {
>       int ret, cpu;
>       unsigned long logical_proc_id_mask = 0; @@ -332,7 +332,7 @@ static
> inline int msr_enable(bool enable)
>       return 0;
>  }
>
> -static int shmem_enable(bool enable)
> +static int shmem_cppc_enable(bool enable)
>  {
>       int cpu, ret = 0;
>       struct cppc_perf_ctrls perf_ctrls;
> @@ -359,11 +359,11 @@ static int shmem_enable(bool enable)
>       return ret;
>  }
>
> -DEFINE_STATIC_CALL(amd_pstate_enable, msr_enable);
> +DEFINE_STATIC_CALL(amd_pstate_cppc_enable, msr_cppc_enable);
>
> -static inline int amd_pstate_enable(bool enable)
> +static inline int amd_pstate_cppc_enable(bool enable)
>  {
> -     return static_call(amd_pstate_enable)(enable);
> +     return static_call(amd_pstate_cppc_enable)(enable);
>  }
>
>  static int msr_init_perf(struct amd_cpudata *cpudata) @@ -1042,7 +1042,7 @@
> static int amd_pstate_cpu_resume(struct cpufreq_policy *policy)  {
>       int ret;
>
> -     ret = amd_pstate_enable(true);
> +     ret = amd_pstate_cppc_enable(true);
>       if (ret)
>               pr_err("failed to enable amd-pstate during resume, return %d\n", ret);
>
> @@ -1053,7 +1053,7 @@ static int amd_pstate_cpu_suspend(struct
> cpufreq_policy *policy)  {
>       int ret;
>
> -     ret = amd_pstate_enable(false);
> +     ret = amd_pstate_cppc_enable(false);
>       if (ret)
>               pr_err("failed to disable amd-pstate during suspend, return %d\n",
> ret);
>
> @@ -1186,7 +1186,7 @@ static ssize_t show_energy_performance_preference(
>
>  static void amd_pstate_driver_cleanup(void)  {
> -     amd_pstate_enable(false);
> +     amd_pstate_cppc_enable(false);
>       cppc_state = AMD_PSTATE_DISABLE;
>       current_pstate_driver = NULL;
>  }
> @@ -1220,7 +1220,7 @@ static int amd_pstate_register_driver(int mode)
>
>       cppc_state = mode;
>
> -     ret = amd_pstate_enable(true);
> +     ret = amd_pstate_cppc_enable(true);
>       if (ret) {
>               pr_err("failed to enable cppc during amd-pstate driver registration,
> return %d\n",
>                      ret);
> @@ -1599,7 +1599,7 @@ static void amd_pstate_epp_reenable(struct
> amd_cpudata *cpudata)
>       u64 value, max_perf;
>       int ret;
>
> -     ret = amd_pstate_enable(true);
> +     ret = amd_pstate_cppc_enable(true);
>       if (ret)
>               pr_err("failed to enable amd pstate during resume, return %d\n", ret);
>
> @@ -1686,7 +1686,7 @@ static int amd_pstate_epp_suspend(struct
> cpufreq_policy *policy)
>       cpudata->suspended = true;
>
>       /* disable CPPC in lowlevel firmware */
> -     ret = amd_pstate_enable(false);
> +     ret = amd_pstate_cppc_enable(false);
>       if (ret)
>               pr_err("failed to suspend, return %d\n", ret);
>
> @@ -1861,7 +1861,7 @@ static int __init amd_pstate_init(void)
>                       current_pstate_driver->adjust_perf =
> amd_pstate_adjust_perf;
>       } else {
>               pr_debug("AMD CPPC shared memory based functionality is
> supported\n");
> -             static_call_update(amd_pstate_enable, shmem_enable);
> +             static_call_update(amd_pstate_cppc_enable, shmem_cppc_enable);
>               static_call_update(amd_pstate_init_perf, shmem_init_perf);
>               static_call_update(amd_pstate_update_perf, shmem_update_perf);
>       }
> @@ -1886,7 +1886,7 @@ static int __init amd_pstate_init(void)
>
>  global_attr_free:
>       cpufreq_unregister_driver(current_pstate_driver);
> -     amd_pstate_enable(false);
> +     amd_pstate_cppc_enable(false);
>       return ret;
>  }
>  device_initcall(amd_pstate_init);
> --
> 2.34.1

LGTM, thanks.


Reviewed-by: Perry Yuan <perry.yuan@amd.com>


Best Regards.

Perry.

RE: [PATCH 3/4] cpufreq/amd-pstate: Call cppc_set_epp_perf in the reenable function

[Yuan, Perry]

[AMD Official Use Only - AMD Internal Distribution Only]

> -----Original Message-----
> From: Ugwekar, Dhananjay <Dhananjay.Ugwekar@amd.com>
> Sent: Wednesday, October 23, 2024 6:21 PM
> To: Shenoy, Gautham Ranjal <gautham.shenoy@amd.com>; Limonciello, Mario
> <Mario.Limonciello@amd.com>; Yuan, Perry <Perry.Yuan@amd.com>;
> rafael@kernel.org; viresh.kumar@linaro.org
> Cc: linux-pm@vger.kernel.org; linux-kernel@vger.kernel.org; Ugwekar, Dhananjay
> <Dhananjay.Ugwekar@amd.com>
> Subject: [PATCH 3/4] cpufreq/amd-pstate: Call cppc_set_epp_perf in the reenable
> function
>
> The EPP value being set in perf_ctrls.energy_perf is not being propagated to the
> shared memory, fix that.
>
> Signed-off-by: Dhananjay Ugwekar <Dhananjay.Ugwekar@amd.com>
> ---
>  drivers/cpufreq/amd-pstate.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index
> 576251e61ce0..bbeddce90823 100644
> --- a/drivers/cpufreq/amd-pstate.c
> +++ b/drivers/cpufreq/amd-pstate.c
> @@ -1616,8 +1616,9 @@ static void amd_pstate_epp_reenable(struct
> amd_cpudata *cpudata)
>               wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
>       } else {
>               perf_ctrls.max_perf = max_perf;
> -             perf_ctrls.energy_perf =
> AMD_CPPC_ENERGY_PERF_PREF(cpudata->epp_cached);
>               cppc_set_perf(cpudata->cpu, &perf_ctrls);
> +             perf_ctrls.energy_perf =
> AMD_CPPC_ENERGY_PERF_PREF(cpudata->epp_cached);
> +             cppc_set_epp_perf(cpudata->cpu, &perf_ctrls, 1);
>       }
>  }
>
> @@ -1658,8 +1659,9 @@ static void amd_pstate_epp_offline(struct cpufreq_policy
> *policy)
>       } else {
>               perf_ctrls.desired_perf = 0;
>               perf_ctrls.max_perf = min_perf;
> -             perf_ctrls.energy_perf =
> AMD_CPPC_ENERGY_PERF_PREF(HWP_EPP_BALANCE_POWERSAVE);
>               cppc_set_perf(cpudata->cpu, &perf_ctrls);
> +             perf_ctrls.energy_perf =
> AMD_CPPC_ENERGY_PERF_PREF(HWP_EPP_BALANCE_POWERSAVE);
> +             cppc_set_epp_perf(cpudata->cpu, &perf_ctrls, 1);
>       }
>       mutex_unlock(&amd_pstate_limits_lock);
>  }
> --
> 2.34.1

LGTM, thanks.


Reviewed-by: Perry Yuan <perry.yuan@amd.com>


Best Regards.

Perry.

Re: [PATCH 2/4] cpufreq/amd-pstate: Do not attempt to clear MSR_AMD_CPPC_ENABLE

[Gautham R. Shenoy]

On Wed, Oct 23, 2024 at 10:21:08AM +0000, Dhananjay Ugwekar wrote:
> MSR_AMD_CPPC_ENABLE is a write once register, i.e. attempting to clear
> it is futile, it will not take effect. Hence, return if disable (0)
> argument is passed to the msr_cppc_enable()
> 
> Signed-off-by: Dhananjay Ugwekar <Dhananjay.Ugwekar@amd.com>

Reviewed-by: Gautham R. Shenoy <gautham.shenoy@amd.com>


> ---
>  drivers/cpufreq/amd-pstate.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
> index 0b4a4d69c14d..576251e61ce0 100644
> --- a/drivers/cpufreq/amd-pstate.c
> +++ b/drivers/cpufreq/amd-pstate.c
> @@ -311,6 +311,12 @@ static inline int msr_cppc_enable(bool enable)
>  	int ret, cpu;
>  	unsigned long logical_proc_id_mask = 0;
>  
> +       /*
> +        * MSR_AMD_CPPC_ENABLE is write-once, once set it cannot be cleared.
> +        */
> +	if (!enable)
> +		return 0;
> +
>  	if (enable == cppc_enabled)
>  		return 0;
>  
> -- 
> 2.34.1
> 

Re: [PATCH 3/4] cpufreq/amd-pstate: Call cppc_set_epp_perf in the reenable function

[Gautham R. Shenoy]

On Wed, Oct 23, 2024 at 10:21:10AM +0000, Dhananjay Ugwekar wrote:
> The EPP value being set in perf_ctrls.energy_perf is not being propagated
> to the shared memory, fix that.

Thanks for fixing this.

Reviewed-by: Gautham R. Shenoy <gautham.shenoy@amd.com>

> 
> Signed-off-by: Dhananjay Ugwekar <Dhananjay.Ugwekar@amd.com>
> ---
>  drivers/cpufreq/amd-pstate.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
> index 576251e61ce0..bbeddce90823 100644
> --- a/drivers/cpufreq/amd-pstate.c
> +++ b/drivers/cpufreq/amd-pstate.c
> @@ -1616,8 +1616,9 @@ static void amd_pstate_epp_reenable(struct amd_cpudata *cpudata)
>  		wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
>  	} else {
>  		perf_ctrls.max_perf = max_perf;
> -		perf_ctrls.energy_perf = AMD_CPPC_ENERGY_PERF_PREF(cpudata->epp_cached);
>  		cppc_set_perf(cpudata->cpu, &perf_ctrls);
> +		perf_ctrls.energy_perf = AMD_CPPC_ENERGY_PERF_PREF(cpudata->epp_cached);
> +		cppc_set_epp_perf(cpudata->cpu, &perf_ctrls, 1);
>  	}
>  }
>  
> @@ -1658,8 +1659,9 @@ static void amd_pstate_epp_offline(struct cpufreq_policy *policy)
>  	} else {
>  		perf_ctrls.desired_perf = 0;
>  		perf_ctrls.max_perf = min_perf;
> -		perf_ctrls.energy_perf = AMD_CPPC_ENERGY_PERF_PREF(HWP_EPP_BALANCE_POWERSAVE);
>  		cppc_set_perf(cpudata->cpu, &perf_ctrls);
> +		perf_ctrls.energy_perf = AMD_CPPC_ENERGY_PERF_PREF(HWP_EPP_BALANCE_POWERSAVE);
> +		cppc_set_epp_perf(cpudata->cpu, &perf_ctrls, 1);
>  	}
>  	mutex_unlock(&amd_pstate_limits_lock);
>  }
> -- 
> 2.34.1
> 

Re: [PATCH 4/4] cpufreq/amd-pstate: Align offline flow of shared memory and MSR based systems

[Gautham R. Shenoy]

On Wed, Oct 23, 2024 at 10:21:12AM +0000, Dhananjay Ugwekar wrote:
> Set min_perf to lowest_perf for shared memory systems, similar to the MSR
> based systems.
> 
> Signed-off-by: Dhananjay Ugwekar <Dhananjay.Ugwekar@amd.com>

Thanks for fixing this.

Reviewed-by: Gautham R. Shenoy <gautham.shenoy@amd.com>

--
Thanks and Regards
gautham.

> ---
>  drivers/cpufreq/amd-pstate.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
> index bbeddce90823..206725219d8c 100644
> --- a/drivers/cpufreq/amd-pstate.c
> +++ b/drivers/cpufreq/amd-pstate.c
> @@ -1658,6 +1658,7 @@ static void amd_pstate_epp_offline(struct cpufreq_policy *policy)
>  		wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
>  	} else {
>  		perf_ctrls.desired_perf = 0;
> +		perf_ctrls.min_perf = min_perf;
>  		perf_ctrls.max_perf = min_perf;
>  		cppc_set_perf(cpudata->cpu, &perf_ctrls);
>  		perf_ctrls.energy_perf = AMD_CPPC_ENERGY_PERF_PREF(HWP_EPP_BALANCE_POWERSAVE);
> -- 
> 2.34.1
>