From: "Roger Pau Monné" <roger.pau@citrix.com>
To: "Chen, Jiqian" <Jiqian.Chen@amd.com>
Cc: "xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>,
Andrew Cooper <andrew.cooper3@citrix.com>,
Jan Beulich <jbeulich@suse.com>, Julien Grall <julien@xen.org>,
Stefano Stabellini <sstabellini@kernel.org>
Subject: Re: [PATCH] vpci: Add resizable bar support
Date: Wed, 20 Nov 2024 09:09:48 +0100 [thread overview]
Message-ID: <Zz2ZTD7ugA9MVzjO@macbook> (raw)
In-Reply-To: <BL1PR12MB58495B6D78F5D63180552BACE7212@BL1PR12MB5849.namprd12.prod.outlook.com>
On Wed, Nov 20, 2024 at 02:30:33AM +0000, Chen, Jiqian wrote:
> On 2024/11/19 20:51, Roger Pau Monné wrote:
> > On Wed, Nov 13, 2024 at 04:00:27PM +0800, Jiqian Chen wrote:
> >> +static void cf_check rebar_ctrl_write(const struct pci_dev *pdev,
> >> + unsigned int reg,
> >> + uint32_t val,
> >> + void *data)
> >> +{
> >> + uint32_t ctrl, index;
> >> + struct vpci_bar *bars = pdev->vpci->header.bars;
> >> +
> >> + ctrl = pci_conf_read32(pdev->sbdf, reg);
> >> + if ( ctrl == val )
> >> + return;
> >> +
> >> + ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
> >> + if ( ctrl != ( val & ~PCI_REBAR_CTRL_BAR_SIZE ) )
> >> + return;
> >> +
> >> + index = ctrl & PCI_REBAR_CTRL_BAR_IDX;
> >> + bars[index].size = (1 << ((val & PCI_REBAR_CTRL_BAR_SIZE) >>
> >> + PCI_REBAR_CTRL_BAR_SHIFT)) *
> >> + PCI_REBAR_CTRL_BAR_UNIT;
> >
> > One further comment: you also need to reset addr and guest_addr here
> > (possibly by reading them from the BAR register), as the specification
> > states that:
> How about just set them to 0, since the addr will be re-assigned by system and the addr of BAR register is also out of date.
Seems good, I assume Xen would also get 0 as the BAR register address
after having changed the size.
Thanks, Roger.
prev parent reply other threads:[~2024-11-20 8:10 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-13 8:00 [PATCH] vpci: Add resizable bar support Jiqian Chen
2024-11-13 9:30 ` Roger Pau Monné
2024-11-13 10:00 ` Chen, Jiqian
2024-11-13 10:30 ` Roger Pau Monné
2024-11-13 10:36 ` Jan Beulich
2024-11-13 10:56 ` Roger Pau Monné
2024-11-13 11:01 ` Jan Beulich
2024-11-13 11:24 ` Roger Pau Monné
2024-11-13 11:29 ` Jan Beulich
2024-11-13 12:13 ` Roger Pau Monné
2024-11-14 6:11 ` Chen, Jiqian
2024-11-14 15:52 ` Roger Pau Monné
2024-11-14 17:36 ` Roger Pau Monné
2024-11-15 3:04 ` Chen, Jiqian
2024-11-15 11:42 ` Roger Pau Monné
2024-11-18 6:06 ` Chen, Jiqian
2024-11-19 12:46 ` Roger Pau Monné
2024-11-20 3:01 ` Chen, Jiqian
2024-11-20 9:01 ` Roger Pau Monné
2024-11-20 10:06 ` Jan Beulich
2024-11-20 10:25 ` Chen, Jiqian
2024-11-21 3:05 ` Chen, Jiqian
2024-11-21 9:52 ` Roger Pau Monné
2024-11-22 4:04 ` Chen, Jiqian
2024-11-22 7:58 ` Roger Pau Monné
2024-11-25 3:44 ` Chen, Jiqian
2024-11-25 12:47 ` Roger Pau Monné
2024-11-26 6:02 ` Chen, Jiqian
2024-11-26 9:47 ` Jan Beulich
2024-11-27 9:07 ` Chen, Jiqian
2024-11-15 2:16 ` Chen, Jiqian
2024-11-14 17:58 ` Roger Pau Monné
2024-11-18 10:17 ` Roger Pau Monné
2024-11-18 10:26 ` Jan Beulich
2024-11-18 16:41 ` Stefano Stabellini
2024-11-19 7:31 ` Chen, Jiqian
2024-11-19 7:44 ` Jan Beulich
2024-11-20 2:26 ` Chen, Jiqian
2024-11-20 8:06 ` Roger Pau Monné
2024-11-19 12:51 ` Roger Pau Monné
2024-11-20 2:30 ` Chen, Jiqian
2024-11-20 8:09 ` Roger Pau Monné [this message]
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