[PATCH v3 00/12] multi-target: add hexagon

[PATCH v3 00/12] multi-target: add hexagon

[Pierrick Bouvier]

This series makes hexagon compatible with the other ones we already integrated.

The biggest change is to introduce a semihosting interface, since existing arm
symbols conflict with hexagon ones. This is also need for when we'll integrate
riscv soon.

v3
--

- constify some semihosting operations (now taking a const *cs in parameter).
- edit commit description when using new interface in semihosting
  implementation, to reflect we don't check if semi_ops is NULL.

v2
--

- rebase on top of master (one conflict with helper renaming)

Note: this series is fully reviewed and I'll send it as PR on Friday if there
are no additional comments.

Pierrick Bouvier (12):
  target/hexagon: prefix helpers conflicting with other arch
  target-info: add target_hexagon
  hw/hexagon/virt: make machine available for hexagon target only
  hw/core/cpu: restrict tcg_ops to CONFIG_TCG only
  semihosting: declare semihosting cpu ops
  target/riscv/cpu: constify cpu parameter for riscv_cpu_mxl
  target/riscv: declare semihosting ops
  target/hexagon: declare semihosting ops
  target/arm: declare semihosting ops
  semihosting: use new semihosting ops
  semihosting: remove common_* functions
  meson.build: add hexagon-softmmu to multi-target

 hw/hexagon/virt.c                   |  2 ++
 include/hw/core/cpu.h               |  8 +++++
 include/qemu/target-info.h          |  7 ++++
 include/semihosting/common-semi.h   | 24 +++++++++----
 meson.build                         |  1 +
 semihosting/arm-compat-semi.c       | 56 ++++++++++++++---------------
 target-info.c                       |  5 +++
 target/arm/common-semi-target.c     | 33 +++++++++++------
 target/arm/cpu.c                    |  4 +++
 target/arm/internals.h              |  2 ++
 target/hexagon/common-semi-target.c | 30 ++++++++++------
 target/hexagon/cpu.c                |  2 ++
 target/hexagon/gen_tcg.h            |  2 +-
 target/hexagon/gen_tcg_sys.h        |  2 +-
 target/hexagon/helper.h             |  4 +--
 target/hexagon/hex_mmu.c            |  2 +-
 target/hexagon/hex_mmu.h            |  2 +-
 target/hexagon/internal.h           |  2 ++
 target/hexagon/op_helper.c          |  4 +--
 target/hexagon/translate.c          |  4 +--
 target/riscv/common-semi-target.c   | 37 ++++++++++++-------
 target/riscv/cpu.c                  |  4 +++
 target/riscv/cpu.h                  |  2 +-
 target/riscv/internals.h            |  2 ++
 24 files changed, 161 insertions(+), 80 deletions(-)

-- 
2.43.0

[PATCH v3 01/12] target/hexagon: prefix helpers conflicting with other arch

[Pierrick Bouvier]

Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
 target/hexagon/gen_tcg.h     | 2 +-
 target/hexagon/gen_tcg_sys.h | 2 +-
 target/hexagon/helper.h      | 4 ++--
 target/hexagon/hex_mmu.c     | 2 +-
 target/hexagon/hex_mmu.h     | 2 +-
 target/hexagon/op_helper.c   | 4 ++--
 target/hexagon/translate.c   | 4 ++--
 7 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index 80d8a7b6bac..ed05f97efed 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -1135,7 +1135,7 @@
 #define fGEN_TCG_J2_pause(SHORTCODE) \
     do { \
         uiV = uiV; \
-        gen_helper_raise_exception(tcg_env, \
+        gen_helper_hexagon_raise_exception(tcg_env, \
             tcg_constant_i32(EXCP_YIELD), \
             tcg_constant_i32(ctx->next_PC)); \
     } while (0)
diff --git a/target/hexagon/gen_tcg_sys.h b/target/hexagon/gen_tcg_sys.h
index c9f6b41a877..91ae3421f64 100644
--- a/target/hexagon/gen_tcg_sys.h
+++ b/target/hexagon/gen_tcg_sys.h
@@ -80,7 +80,7 @@
 #define fGEN_TCG_Y2_wait(SHORTCODE) \
     do { \
         RsV = RsV; \
-        gen_helper_wait(tcg_env); \
+        gen_helper_hexagon_wait(tcg_env); \
     } while (0)
 
 #define fGEN_TCG_Y2_resume(SHORTCODE) \
diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h
index 997d87e38e6..b97295f243a 100644
--- a/target/hexagon/helper.h
+++ b/target/hexagon/helper.h
@@ -18,7 +18,7 @@
 #include "internal.h"
 #include "helper_protos_generated.h.inc"
 
-DEF_HELPER_FLAGS_3(raise_exception, TCG_CALL_NO_RETURN, noreturn, env, i32, i32)
+DEF_HELPER_FLAGS_3(hexagon_raise_exception, TCG_CALL_NO_RETURN, noreturn, env, i32, i32)
 DEF_HELPER_2(commit_store, void, env, int)
 DEF_HELPER_3(gather_store, void, env, i32, int)
 DEF_HELPER_1(commit_hvx_stores, void, env)
@@ -136,7 +136,7 @@ DEF_HELPER_3(sreg_write_masked, void, env, i32, i32)
 DEF_HELPER_3(setprio, void, env, i32, i32)
 DEF_HELPER_2(start, void, env, i32)
 DEF_HELPER_1(stop, void, env)
-DEF_HELPER_1(wait, void, env)
+DEF_HELPER_1(hexagon_wait, void, env)
 DEF_HELPER_2(resume, void, env, i32)
 DEF_HELPER_1(resched, void, env)
 DEF_HELPER_3(modify_ssr, void, env, i32, i32)
diff --git a/target/hexagon/hex_mmu.c b/target/hexagon/hex_mmu.c
index 0ca52ed666d..f98585a1d24 100644
--- a/target/hexagon/hex_mmu.c
+++ b/target/hexagon/hex_mmu.c
@@ -115,7 +115,7 @@ int hex_tlb_check_overlap(CPUHexagonState *env, uint64_t entry, uint64_t index)
 }
 
 #ifdef CONFIG_HMP
-void dump_mmu(MonitorHMP *hmp, CPUHexagonState *env)
+void hexagon_dump_mmu(MonitorHMP *hmp, CPUHexagonState *env)
 {
     HexagonCPU *cpu = env_archcpu(env);
     hexagon_tlb_dump(hmp, cpu->tlb);
diff --git a/target/hexagon/hex_mmu.h b/target/hexagon/hex_mmu.h
index 977a97da31a..2cfcd10949a 100644
--- a/target/hexagon/hex_mmu.h
+++ b/target/hexagon/hex_mmu.h
@@ -24,5 +24,5 @@ extern int hex_tlb_check_overlap(CPUHexagonState *env, uint64_t entry,
                                  uint64_t index);
 extern void hex_tlb_lock(CPUHexagonState *env, uint32_t PC);
 extern void hex_tlb_unlock(CPUHexagonState *env);
-void dump_mmu(MonitorHMP *hmp, CPUHexagonState *env);
+void hexagon_dump_mmu(MonitorHMP *hmp, CPUHexagonState *env);
 #endif
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index accadd7927a..199a2827f96 100644
--- a/target/hexagon/op_helper.c
+++ b/target/hexagon/op_helper.c
@@ -93,7 +93,7 @@ G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env,
     do_raise_exception(env, exception, pc, 0);
 }
 
-G_NORETURN void HELPER(raise_exception)(CPUHexagonState *env, uint32_t excp,
+G_NORETURN void HELPER(hexagon_raise_exception)(CPUHexagonState *env, uint32_t excp,
                                         uint32_t PC)
 {
     hexagon_raise_exception_err(env, excp, PC);
@@ -1837,7 +1837,7 @@ void HELPER(resched)(CPUHexagonState *env)
     resched(env);
 }
 
-void HELPER(wait)(CPUHexagonState *env)
+void HELPER(hexagon_wait)(CPUHexagonState *env)
 {
     BQL_LOCK_GUARD();
 
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index cd1abdf1461..ee8588e0677 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -140,7 +140,7 @@ intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum,
 static void gen_precise_exception(int cause, uint32_t PC)
 {
     tcg_gen_movi_i32(hex_cause_code, cause);
-    gen_helper_raise_exception(tcg_env, tcg_constant_i32(HEX_EVENT_PRECISE),
+    gen_helper_hexagon_raise_exception(tcg_env, tcg_constant_i32(HEX_EVENT_PRECISE),
                                tcg_constant_i32(PC));
 }
 
@@ -1163,7 +1163,7 @@ static void check_imprecise_exception(DisasContext *ctx)
     TCGLabel *label = gen_new_label();
 
     tcg_gen_brcondi_tl(TCG_COND_EQ, hex_imprecise_exception, 0, label);
-    gen_helper_raise_exception(tcg_env, hex_imprecise_exception, PC);
+    gen_helper_hexagon_raise_exception(tcg_env, hex_imprecise_exception, PC);
     gen_set_label(label);
 }
 #endif
-- 
2.43.0

[PATCH v3 02/12] target-info: add target_hexagon

[Pierrick Bouvier]

Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
 include/qemu/target-info.h | 7 +++++++
 target-info.c              | 5 +++++
 2 files changed, 12 insertions(+)

diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h
index adda363ac39..862097c6c63 100644
--- a/include/qemu/target-info.h
+++ b/include/qemu/target-info.h
@@ -70,6 +70,13 @@ bool target_aarch64(void);
  */
 bool target_m68k(void);
 
+/**
+ * target_hexagon:
+ *
+ * Returns whether the target architecture is Hexagon.
+ */
+bool target_hexagon(void);
+
 /**
  * target_or1k:
  *
diff --git a/target-info.c b/target-info.c
index 6b365113955..254530d8ea5 100644
--- a/target-info.c
+++ b/target-info.c
@@ -68,6 +68,11 @@ bool target_m68k(void)
     return target_arch() == SYS_EMU_TARGET_M68K;
 }
 
+bool target_hexagon(void)
+{
+    return target_arch() == SYS_EMU_TARGET_HEXAGON;
+}
+
 bool target_or1k(void)
 {
     return target_arch() == SYS_EMU_TARGET_OR1K;
-- 
2.43.0

[PATCH v3 03/12] hw/hexagon/virt: make machine available for hexagon target only

[Pierrick Bouvier]

Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
 hw/hexagon/virt.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/hw/hexagon/virt.c b/hw/hexagon/virt.c
index 64d8366d27d..b601cd77a92 100644
--- a/hw/hexagon/virt.c
+++ b/hw/hexagon/virt.c
@@ -20,6 +20,7 @@
 #include "hw/core/register.h"
 #include "qemu/error-report.h"
 #include "qemu/guest-random.h"
+#include "qemu/target-info.h"
 #include "qemu/units.h"
 #include "machine_cfg_v68n_1024.h.inc"
 #include "system/address-spaces.h"
@@ -379,6 +380,7 @@ static const TypeInfo virt_machine_types[] = { {
     .parent = TYPE_HEXAGON_COMMON_MACHINE,
     .instance_size = sizeof(HexagonVirtMachineState),
     .class_init = virt_class_init,
+    .is_available = target_hexagon,
 } };
 
 DEFINE_TYPES(virt_machine_types)
-- 
2.43.0

[PATCH v3 04/12] hw/core/cpu: restrict tcg_ops to CONFIG_TCG only

[Pierrick Bouvier]

We introduce this since upcoming semihosting ops will be in the same
ifdef.

Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
 include/hw/core/cpu.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index ae66f5e33e3..76801444a16 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -183,8 +183,10 @@ struct CPUClass {
     /* when system emulation is not available, this pointer is NULL */
     const struct SysemuCPUOps *sysemu_ops;
 
+#ifdef CONFIG_TCG
     /* when TCG is not available, this pointer is NULL */
     const TCGCPUOps *tcg_ops;
+#endif
 
     /*
      * Keep non-pointer data at the end to minimize holes.
-- 
2.43.0

[PATCH v3 05/12] semihosting: declare semihosting cpu ops

[Pierrick Bouvier]

This allows a specific target to declare its implementation of
semihosting.

Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
 include/hw/core/cpu.h             |  6 ++++++
 include/semihosting/common-semi.h | 17 +++++++++++++++++
 2 files changed, 23 insertions(+)

diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 76801444a16..456154df6f6 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -98,6 +98,9 @@ struct AccelCPUClass;
 /* see sysemu-cpu-ops.h */
 struct SysemuCPUOps;
 
+/* see semihosting/common-semi.h */
+struct SemihostingCPUOps;
+
 /**
  * CPUClass:
  * @class_by_name: Callback to map -cpu command line model name to an
@@ -186,6 +189,9 @@ struct CPUClass {
 #ifdef CONFIG_TCG
     /* when TCG is not available, this pointer is NULL */
     const TCGCPUOps *tcg_ops;
+
+    /* when target does not implement semihosting, this pointer is NULL */
+    const struct SemihostingCPUOps *semi_ops;
 #endif
 
     /*
diff --git a/include/semihosting/common-semi.h b/include/semihosting/common-semi.h
index 1e7699d7bbd..f0f8185d8e6 100644
--- a/include/semihosting/common-semi.h
+++ b/include/semihosting/common-semi.h
@@ -34,6 +34,23 @@
 #ifndef COMMON_SEMI_H
 #define COMMON_SEMI_H
 
+typedef struct SemihostingCPUOps {
+    /* Return argument @argno */
+    uint64_t (*arg)(const CPUState *cs, int argno);
+    /* Set return value for semihosting call */
+    void (*set_ret)(CPUState *cs, uint64_t ret);
+    /* Set an error for a semihosting call */
+    void (*set_err)(CPUState *cs, int err);
+    /* True if the guest is using the 64-bit semihosting ABI */
+    bool (*is_64bit)(const CPUState *cs);
+    /* True if SYS_EXIT takes an extended parameter block */
+    bool (*sys_exit_is_extended)(const CPUState *cs);
+    /* Return lowest address until which stack can grow */
+    uint64_t (*stack_bottom)(const CPUState *cs);
+    /* True if SYS_SYNCCACHE is implemented */
+    bool (*has_synccache)(const CPUState *cs);
+} SemihostingCPUOps;
+
 void common_semi_cb(CPUState *cs, uint64_t ret, int err);
 void do_common_semihosting(CPUState *cs);
 uint64_t common_semi_arg(CPUState *cs, int argno);
-- 
2.43.0

[PATCH v3 06/12] target/riscv/cpu: constify cpu parameter for riscv_cpu_mxl

[Pierrick Bouvier]

Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
 target/riscv/cpu.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 8c8ffe94cd8..00650a66dcb 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -755,7 +755,7 @@ FIELD(EXT_TB_FLAGS, BIG_ENDIAN, 33, 1)
 #ifdef TARGET_RISCV32
 #define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
 #else
-static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
+static inline RISCVMXL riscv_cpu_mxl(const CPURISCVState *env)
 {
     return env->misa_mxl;
 }
-- 
2.43.0

[PATCH v3 07/12] target/riscv: declare semihosting ops

[Pierrick Bouvier]

For now, we keep the global common_* symbols defined.

Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
 target/riscv/common-semi-target.c | 66 ++++++++++++++++++++++++++-----
 target/riscv/cpu.c                |  4 ++
 target/riscv/internals.h          |  2 +
 3 files changed, 62 insertions(+), 10 deletions(-)

diff --git a/target/riscv/common-semi-target.c b/target/riscv/common-semi-target.c
index 38a00e160c3..f0f9e29dc4c 100644
--- a/target/riscv/common-semi-target.c
+++ b/target/riscv/common-semi-target.c
@@ -11,43 +11,89 @@
 #include "qemu/osdep.h"
 #include "cpu.h"
 #include "semihosting/common-semi.h"
+#include "internals.h"
 
-uint64_t common_semi_arg(CPUState *cs, int argno)
+static uint64_t riscv_semi_arg(const CPUState *cs, int argno)
 {
-    RISCVCPU *cpu = RISCV_CPU(cs);
-    CPURISCVState *env = &cpu->env;
+    const RISCVCPU *cpu = RISCV_CPU(cs);
+    const CPURISCVState *env = &cpu->env;
     return env->gpr[xA0 + argno];
 }
 
-void common_semi_set_ret(CPUState *cs, uint64_t ret)
+static void riscv_semi_set_ret(CPUState *cs, uint64_t ret)
 {
     RISCVCPU *cpu = RISCV_CPU(cs);
     CPURISCVState *env = &cpu->env;
     env->gpr[xA0] = ret;
 }
 
+static void riscv_semi_set_err(CPUState *cs, int err)
+{
+}
+
+static bool riscv_semi_is_64bit(const CPUState *cs)
+{
+    return riscv_cpu_mxl(cpu_env(cs)) != MXL_RV32;
+}
+
+static bool riscv_semi_sys_exit_is_extended(const CPUState *cs)
+{
+    return riscv_semi_is_64bit(cs);
+}
+
+static uint64_t riscv_semi_stack_bottom(const CPUState *cs)
+{
+    const RISCVCPU *cpu = RISCV_CPU(cs);
+    const CPURISCVState *env = &cpu->env;
+    return env->gpr[xSP];
+}
+
+static bool riscv_semi_has_synccache(const CPUState *cs)
+{
+    return true;
+}
+
+const SemihostingCPUOps riscv_semihosting_ops = {
+    .arg = riscv_semi_arg,
+    .set_ret = riscv_semi_set_ret,
+    .set_err = riscv_semi_set_err,
+    .is_64bit = riscv_semi_is_64bit,
+    .sys_exit_is_extended = riscv_semi_sys_exit_is_extended,
+    .stack_bottom = riscv_semi_stack_bottom,
+    .has_synccache = riscv_semi_has_synccache,
+};
+
+uint64_t common_semi_arg(CPUState *cs, int argno)
+{
+    return riscv_semi_arg(cs, argno);
+}
+
+void common_semi_set_ret(CPUState *cs, uint64_t ret)
+{
+    riscv_semi_set_ret(cs, ret);
+}
+
 void common_semi_set_err(CPUState *cs, int err)
 {
+    riscv_semi_set_err(cs, err);
 }
 
 bool is_64bit_semihosting(CPUArchState *env)
 {
-    return riscv_cpu_mxl(env) != MXL_RV32;
+    return riscv_semi_is_64bit(env_cpu(env));
 }
 
 bool common_semi_sys_exit_is_extended(CPUState *cs)
 {
-    return is_64bit_semihosting(cpu_env(cs));
+    return riscv_semi_sys_exit_is_extended(cs);
 }
 
 uint64_t common_semi_stack_bottom(CPUState *cs)
 {
-    RISCVCPU *cpu = RISCV_CPU(cs);
-    CPURISCVState *env = &cpu->env;
-    return env->gpr[xSP];
+    return riscv_semi_stack_bottom(cs);
 }
 
 bool common_semi_has_synccache(CPUArchState *env)
 {
-    return true;
+    return riscv_semi_has_synccache(env_cpu(env));
 }
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index da4c1a090b9..63c709ac738 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -3053,6 +3053,10 @@ static void riscv_cpu_common_class_init(ObjectClass *c, const void *data)
     cc->gdb_arch_name = riscv_gdb_arch_name;
 #ifdef CONFIG_TCG
     cc->tcg_ops = &riscv_tcg_ops;
+#if !defined(CONFIG_USER_ONLY) || defined(CONFIG_LINUX)
+    /* semihosting is not supported for bsd-user */
+    cc->semi_ops = &riscv_semihosting_ops;
+#endif
 #endif /* CONFIG_TCG */
 
     device_class_set_props(dc, riscv_cpu_properties);
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index 5d84e4de960..f17d011d22f 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -206,6 +206,8 @@ static inline target_ulong get_xepc_mask(CPURISCVState *env)
 bool riscv_cpu_has_work(CPUState *cs);
 #endif
 
+extern const struct SemihostingCPUOps riscv_semihosting_ops;
+
 /* Zjpm addr masking routine */
 static inline target_ulong adjust_addr_body(CPURISCVState *env,
                                             target_ulong addr,
-- 
2.43.0

[PATCH v3 08/12] target/hexagon: declare semihosting ops

[Pierrick Bouvier]

For now, we keep the global common_* symbols defined.

Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
 target/hexagon/common-semi-target.c | 65 ++++++++++++++++++++++++-----
 target/hexagon/cpu.c                |  2 +
 target/hexagon/internal.h           |  2 +
 3 files changed, 59 insertions(+), 10 deletions(-)

diff --git a/target/hexagon/common-semi-target.c b/target/hexagon/common-semi-target.c
index 210d33e54e2..da92ff298a2 100644
--- a/target/hexagon/common-semi-target.c
+++ b/target/hexagon/common-semi-target.c
@@ -8,44 +8,89 @@
 
 #include "qemu/osdep.h"
 #include "cpu.h"
-#include "cpu_helper.h"
 #include "semihosting/common-semi.h"
+#include "internal.h"
 
-uint64_t common_semi_arg(CPUState *cs, int argno)
+static uint64_t hexagon_semi_arg(const CPUState *cs, int argno)
 {
-    CPUHexagonState *env = cpu_env(cs);
+    const CPUHexagonState *env = cpu_env(cs);
     return env->gpr[HEX_REG_R00 + argno];
 }
 
-void common_semi_set_ret(CPUState *cs, uint64_t ret)
+static void hexagon_semi_set_ret(CPUState *cs, uint64_t ret)
 {
     CPUHexagonState *env = cpu_env(cs);
     env->gpr[HEX_REG_R00] = ret;
 }
 
-void common_semi_set_err(CPUState *cs, int err)
+static void hexagon_semi_set_err(CPUState *cs, int err)
 {
     CPUHexagonState *env = cpu_env(cs);
     env->gpr[HEX_REG_R01] = err;
 }
 
-bool common_semi_sys_exit_is_extended(CPUState *cs)
+static bool hexagon_semi_is_64bit(const CPUState *cs)
 {
     return false;
 }
 
+static bool hexagon_semi_sys_exit_is_extended(const CPUState *cs)
+{
+    return false;
+}
+
+static uint64_t hexagon_semi_stack_bottom(const CPUState *cs)
+{
+    const CPUHexagonState *env = cpu_env(cs);
+    return env->gpr[HEX_REG_SP];
+}
+
+static bool hexagon_semi_has_synccache(const CPUState *cs)
+{
+    return false;
+}
+
+const SemihostingCPUOps hexagon_semihosting_ops = {
+    .arg = hexagon_semi_arg,
+    .set_ret = hexagon_semi_set_ret,
+    .set_err = hexagon_semi_set_err,
+    .is_64bit = hexagon_semi_is_64bit,
+    .sys_exit_is_extended = hexagon_semi_sys_exit_is_extended,
+    .stack_bottom = hexagon_semi_stack_bottom,
+    .has_synccache = hexagon_semi_has_synccache,
+};
+
+uint64_t common_semi_arg(CPUState *cs, int argno)
+{
+    return hexagon_semi_arg(cs, argno);
+}
+
+void common_semi_set_ret(CPUState *cs, uint64_t ret)
+{
+    hexagon_semi_set_ret(cs, ret);
+}
+
+void common_semi_set_err(CPUState *cs, int err)
+{
+    hexagon_semi_set_err(cs, err);
+}
+
 bool is_64bit_semihosting(CPUArchState *env)
 {
-    return false;
+    return hexagon_semi_is_64bit(env_cpu(env));
+}
+
+bool common_semi_sys_exit_is_extended(CPUState *cs)
+{
+    return hexagon_semi_sys_exit_is_extended(cs);
 }
 
 uint64_t common_semi_stack_bottom(CPUState *cs)
 {
-    CPUHexagonState *env = cpu_env(cs);
-    return env->gpr[HEX_REG_SP];
+    return hexagon_semi_stack_bottom(cs);
 }
 
 bool common_semi_has_synccache(CPUArchState *env)
 {
-    return false;
+    return hexagon_semi_has_synccache(env_cpu(env));
 }
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 6550e7fa800..8bbd4647968 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -851,6 +851,8 @@ static void hexagon_cpu_class_init(ObjectClass *c, const void *data)
 #ifndef CONFIG_USER_ONLY
     cc->sysemu_ops = &hexagon_sysemu_ops;
     dc->vmsd = &vmstate_hexagon_cpu;
+    /* semihosting is only supported in system mode for Hexagon */
+    cc->semi_ops = &hexagon_semihosting_ops;
 #endif
 #ifdef CONFIG_TCG
     cc->tcg_ops = &hexagon_tcg_ops;
diff --git a/target/hexagon/internal.h b/target/hexagon/internal.h
index 3ed83904eb7..073de10284e 100644
--- a/target/hexagon/internal.h
+++ b/target/hexagon/internal.h
@@ -34,6 +34,8 @@ void hexagon_debug_qreg(CPUHexagonState *env, int regnum);
 void hexagon_debug(CPUHexagonState *env);
 void hexagon_dump(CPUHexagonState *env, FILE *f, int flags);
 
+extern const struct SemihostingCPUOps hexagon_semihosting_ops;
+
 extern const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS];
 #ifndef CONFIG_USER_ONLY
 extern const char * const hexagon_sregnames[];
-- 
2.43.0

[PATCH v3 09/12] target/arm: declare semihosting ops

[Pierrick Bouvier]

For now, we keep the global common_* symbols defined.

Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
 target/arm/common-semi-target.c | 72 +++++++++++++++++++++++++++------
 target/arm/cpu.c                |  4 ++
 target/arm/internals.h          |  2 +
 3 files changed, 65 insertions(+), 13 deletions(-)

diff --git a/target/arm/common-semi-target.c b/target/arm/common-semi-target.c
index 38d52deb3d6..dc5f277a59e 100644
--- a/target/arm/common-semi-target.c
+++ b/target/arm/common-semi-target.c
@@ -10,9 +10,10 @@
 #include "qemu/osdep.h"
 #include "cpu.h"
 #include "semihosting/common-semi.h"
+#include "internals.h"
 #include "target/arm/cpu-qom.h"
 
-uint64_t common_semi_arg(CPUState *cs, int argno)
+static uint64_t arm_semi_arg(const CPUState *cs, int argno)
 {
     ARMCPU *cpu = ARM_CPU(cs);
     CPUARMState *env = &cpu->env;
@@ -23,7 +24,7 @@ uint64_t common_semi_arg(CPUState *cs, int argno)
     }
 }
 
-void common_semi_set_ret(CPUState *cs, uint64_t ret)
+static void arm_semi_set_ret(CPUState *cs, uint64_t ret)
 {
     ARMCPU *cpu = ARM_CPU(cs);
     CPUARMState *env = &cpu->env;
@@ -34,29 +35,74 @@ void common_semi_set_ret(CPUState *cs, uint64_t ret)
     }
 }
 
+static void arm_semi_set_err(CPUState *cs, int err)
+{
+}
+
+static bool arm_semi_is_64bit(const CPUState *cs)
+{
+    return is_a64(cpu_env(cs));
+}
+
+static bool arm_semi_sys_exit_is_extended(const CPUState *cs)
+{
+    return is_a64(cpu_env(cs));
+}
+
+static uint64_t arm_semi_stack_bottom(const CPUState *cs)
+{
+    const ARMCPU *cpu = ARM_CPU(cs);
+    const CPUARMState *env = &cpu->env;
+    return is_a64(env) ? env->xregs[31] : env->regs[13];
+}
+
+static bool arm_semi_has_synccache(const CPUState *cs)
+{
+    /* Ok for A64, invalid for A32/T32 */
+    return is_a64(cpu_env(cs));
+}
+
+const SemihostingCPUOps arm_semihosting_ops = {
+    .arg = arm_semi_arg,
+    .set_ret = arm_semi_set_ret,
+    .set_err = arm_semi_set_err,
+    .is_64bit = arm_semi_is_64bit,
+    .sys_exit_is_extended = arm_semi_sys_exit_is_extended,
+    .stack_bottom = arm_semi_stack_bottom,
+    .has_synccache = arm_semi_has_synccache,
+};
+
+uint64_t common_semi_arg(CPUState *cs, int argno)
+{
+    return arm_semi_arg(cs, argno);
+}
+
+void common_semi_set_ret(CPUState *cs, uint64_t ret)
+{
+    arm_semi_set_ret(cs, ret);
+}
+
 void common_semi_set_err(CPUState *cs, int err)
 {
-}
-
-bool common_semi_sys_exit_is_extended(CPUState *cs)
-{
-    return is_a64(cpu_env(cs));
+    arm_semi_set_err(cs, err);
 }
 
 bool is_64bit_semihosting(CPUArchState *env)
 {
-    return is_a64(env);
+    return arm_semi_is_64bit(env_cpu(env));
+}
+
+bool common_semi_sys_exit_is_extended(CPUState *cs)
+{
+    return arm_semi_sys_exit_is_extended(cs);
 }
 
 uint64_t common_semi_stack_bottom(CPUState *cs)
 {
-    ARMCPU *cpu = ARM_CPU(cs);
-    CPUARMState *env = &cpu->env;
-    return is_a64(env) ? env->xregs[31] : env->regs[13];
+    return arm_semi_stack_bottom(cs);
 }
 
 bool common_semi_has_synccache(CPUArchState *env)
 {
-    /* Ok for A64, invalid for A32/T32 */
-    return is_a64(env);
+    return arm_semi_has_synccache(env_cpu(env));
 }
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 10ac6c98318..81ec1ce21c6 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2663,6 +2663,10 @@ static void arm_cpu_class_init(ObjectClass *oc, const void *data)
 
 #ifdef CONFIG_TCG
     cc->tcg_ops = &arm_tcg_ops;
+#if !defined(CONFIG_USER_ONLY) || defined(CONFIG_LINUX)
+    /* semihosting is not supported for bsd-user */
+    cc->semi_ops = &arm_semihosting_ops;
+#endif
 #endif /* CONFIG_TCG */
 }
 
diff --git a/target/arm/internals.h b/target/arm/internals.h
index c41fa5225c7..e849e357cfe 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -437,6 +437,8 @@ bool arm_cpu_exec_halt(CPUState *cs);
 int arm_cpu_mmu_index(CPUState *cs, bool ifetch);
 #endif /* CONFIG_TCG */
 
+extern const struct SemihostingCPUOps arm_semihosting_ops;
+
 typedef enum ARMFPRounding {
     FPROUNDING_TIEEVEN,
     FPROUNDING_POSINF,
-- 
2.43.0

[PATCH v3 10/12] semihosting: use new semihosting ops

[Pierrick Bouvier]

Now that all targets implement this interface, we can replace function
calls with the new interface.

We assume semihosting ops are set on this code path, and do not perform
a NULL check.

Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
 semihosting/arm-compat-semi.c | 56 +++++++++++++++++------------------
 1 file changed, 28 insertions(+), 28 deletions(-)

diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c
index b930a028649..3117eadb3b7 100644
--- a/semihosting/arm-compat-semi.c
+++ b/semihosting/arm-compat-semi.c
@@ -188,7 +188,7 @@ static LayoutInfo common_semi_find_bases(CPUState *cs)
  */
 
 #define GET_ARG(n) do {                                 \
-    if (is_64bit_semihosting(env)) {                    \
+    if (cs->cc->semi_ops->is_64bit(cs)) {               \
         if (get_user_u64(arg ## n, args + (n) * 8)) {   \
             goto do_fault;                              \
         }                                               \
@@ -200,7 +200,7 @@ static LayoutInfo common_semi_find_bases(CPUState *cs)
 } while (0)
 
 #define SET_ARG(n, val)                                 \
-    (is_64bit_semihosting(env) ?                        \
+    (cs->cc->semi_ops->is_64bit(cs) ?                   \
      put_user_u64(val, args + (n) * 8) :                \
      put_user_u32(val, args + (n) * 4))
 
@@ -237,10 +237,10 @@ void common_semi_cb(CPUState *cs, uint64_t ret, int err)
         ts->swi_errno = err;
 #else
         syscall_err = err;
-        common_semi_set_err(cs, err);
+        cs->cc->semi_ops->set_err(cs, err);
 #endif
     }
-    common_semi_set_ret(cs, ret);
+    cs->cc->semi_ops->set_ret(cs, ret);
 }
 
 /*
@@ -249,7 +249,7 @@ void common_semi_cb(CPUState *cs, uint64_t ret, int err)
  */
 static void common_semi_dead_cb(CPUState *cs, uint64_t ret, int err)
 {
-    common_semi_set_ret(cs, 0xdeadbeef);
+    cs->cc->semi_ops->set_ret(cs, 0xdeadbeef);
 }
 
 /*
@@ -260,7 +260,7 @@ static void common_semi_rw_cb(CPUState *cs, uint64_t ret, int err)
 {
     /* Recover the original length from the third argument. */
     CPUArchState *env G_GNUC_UNUSED = cpu_env(cs);
-    uint64_t args = common_semi_arg(cs, 1);
+    uint64_t args = cs->cc->semi_ops->arg(cs, 1);
     uint64_t arg2;
     GET_ARG(2);
 
@@ -268,7 +268,7 @@ static void common_semi_rw_cb(CPUState *cs, uint64_t ret, int err)
  do_fault:
         ret = 0; /* error: no bytes transmitted */
     }
-    common_semi_set_ret(cs, arg2 - ret);
+    cs->cc->semi_ops->set_ret(cs, arg2 - ret);
 }
 
 /*
@@ -302,7 +302,7 @@ static void common_semi_seek_cb(CPUState *cs, uint64_t ret, int err)
  */
 static uint64_t common_semi_flen_buf(CPUState *cs)
 {
-    vaddr sp = common_semi_stack_bottom(cs);
+    vaddr sp = cs->cc->semi_ops->stack_bottom(cs);
     return sp - 64;
 }
 
@@ -330,7 +330,7 @@ common_semi_readc_cb(CPUState *cs, uint64_t ret, int err)
         CPUArchState *env G_GNUC_UNUSED = cpu_env(cs);
         uint8_t ch;
 
-        if (get_user_u8(ch, common_semi_stack_bottom(cs) - 1)) {
+        if (get_user_u8(ch, cs->cc->semi_ops->stack_bottom(cs) - 1)) {
             ret = -1, err = EFAULT;
         } else {
             ret = ch;
@@ -385,7 +385,7 @@ void semihosting_arm_compatible_init(void)
  */
 void do_common_semihosting(CPUState *cs)
 {
-    CPUArchState *env = cpu_env(cs);
+    CPUArchState *env G_GNUC_UNUSED = cpu_env(cs);
     uint64_t args;
     uint64_t arg0, arg1, arg2, arg3;
     uint64_t ul_ret;
@@ -393,8 +393,8 @@ void do_common_semihosting(CPUState *cs)
     int nr;
     int64_t elapsed;
 
-    nr = common_semi_arg(cs, 0) & 0xffffffffU;
-    args = common_semi_arg(cs, 1);
+    nr = cs->cc->semi_ops->arg(cs, 0) & 0xffffffffU;
+    args = cs->cc->semi_ops->arg(cs, 1);
 
     switch (nr) {
     case TARGET_SYS_OPEN:
@@ -494,15 +494,15 @@ void do_common_semihosting(CPUState *cs)
 
     case TARGET_SYS_READC:
         semihost_sys_read_gf(cs, common_semi_readc_cb, &console_in_gf,
-                             common_semi_stack_bottom(cs) - 1, 1);
+                             cs->cc->semi_ops->stack_bottom(cs) - 1, 1);
         break;
 
     case TARGET_SYS_ISERROR:
     {
         GET_ARG(0);
-        bool ret = is_64bit_semihosting(env) ?
+        bool ret = cs->cc->semi_ops->is_64bit(cs) ?
                    (int64_t)arg0 < 0 : (int32_t)arg0 < 0;
-        common_semi_set_ret(cs, ret);
+        cs->cc->semi_ops->set_ret(cs, ret);
         break;
     }
     case TARGET_SYS_ISTTY:
@@ -533,7 +533,7 @@ void do_common_semihosting(CPUState *cs)
         len = asprintf(&s, "%s/qemu-%x%02x", g_get_tmp_dir(),
                        getpid(), (int)arg1 & 0xff);
         if (len < 0) {
-            common_semi_set_ret(cs, -1);
+            cs->cc->semi_ops->set_ret(cs, -1);
             break;
         }
 
@@ -542,7 +542,7 @@ void do_common_semihosting(CPUState *cs)
         /* Make sure there's enough space in the buffer */
         if (len > arg2) {
             free(s);
-            common_semi_set_ret(cs, -1);
+            cs->cc->semi_ops->set_ret(cs, -1);
             break;
         }
         p = lock_user(VERIFY_WRITE, arg0, len, 0);
@@ -553,7 +553,7 @@ void do_common_semihosting(CPUState *cs)
         memcpy(p, s, len);
         unlock_user(p, arg0, len);
         free(s);
-        common_semi_set_ret(cs, 0);
+        cs->cc->semi_ops->set_ret(cs, 0);
         break;
     }
 
@@ -572,7 +572,7 @@ void do_common_semihosting(CPUState *cs)
         break;
 
     case TARGET_SYS_CLOCK:
-        common_semi_set_ret(cs, clock() / (CLOCKS_PER_SEC / 100));
+        cs->cc->semi_ops->set_ret(cs, clock() / (CLOCKS_PER_SEC / 100));
         break;
 
     case TARGET_SYS_TIME:
@@ -587,7 +587,7 @@ void do_common_semihosting(CPUState *cs)
         break;
 
     case TARGET_SYS_ERRNO:
-        common_semi_set_ret(cs, get_swi_errno(cs));
+        cs->cc->semi_ops->set_ret(cs, get_swi_errno(cs));
         break;
 
     case TARGET_SYS_GET_CMDLINE:
@@ -734,7 +734,7 @@ void do_common_semihosting(CPUState *cs)
             for (i = 0; i < ARRAY_SIZE(retvals); i++) {
                 bool fail;
 
-                if (is_64bit_semihosting(env)) {
+                if (cs->cc->semi_ops->is_64bit(cs)) {
                     fail = put_user_u64(retvals[i], arg0 + i * 8);
                 } else {
                     fail = put_user_u32(retvals[i], arg0 + i * 4);
@@ -745,7 +745,7 @@ void do_common_semihosting(CPUState *cs)
                     goto do_fault;
                 }
             }
-            common_semi_set_ret(cs, 0);
+            cs->cc->semi_ops->set_ret(cs, 0);
         }
         break;
 
@@ -755,7 +755,7 @@ void do_common_semihosting(CPUState *cs)
         uint32_t ret;
 
         if (nr == TARGET_SYS_EXIT_EXTENDED ||
-            common_semi_sys_exit_is_extended(cs)) {
+            cs->cc->semi_ops->sys_exit_is_extended(cs)) {
             /*
              * The A64 version of SYS_EXIT takes a parameter block,
              * so the application-exit type can return a subcode which
@@ -786,7 +786,7 @@ void do_common_semihosting(CPUState *cs)
 
     case TARGET_SYS_ELAPSED:
         elapsed = get_clock() - clock_start;
-        if (is_64bit_semihosting(env)) {
+        if (cs->cc->semi_ops->is_64bit(cs)) {
             if (SET_ARG(0, elapsed)) {
                 goto do_fault;
             }
@@ -796,12 +796,12 @@ void do_common_semihosting(CPUState *cs)
                 goto do_fault;
             }
         }
-        common_semi_set_ret(cs, 0);
+        cs->cc->semi_ops->set_ret(cs, 0);
         break;
 
     case TARGET_SYS_TICKFREQ:
         /* qemu always uses nsec */
-        common_semi_set_ret(cs, 1000000000);
+        cs->cc->semi_ops->set_ret(cs, 1000000000);
         break;
 
     case TARGET_SYS_SYNCCACHE:
@@ -810,8 +810,8 @@ void do_common_semihosting(CPUState *cs)
          * virtual address range. This is a nop for us since we don't
          * implement caches. This is only present on A64.
          */
-        if (common_semi_has_synccache(env)) {
-            common_semi_set_ret(cs, 0);
+        if (cs->cc->semi_ops->has_synccache(cs)) {
+            cs->cc->semi_ops->set_ret(cs, 0);
             break;
         }
         /* fall through */
-- 
2.43.0

[PATCH v3 11/12] semihosting: remove common_* functions

[Pierrick Bouvier]

Now that both targets and semihosting implementation both use the
semihosting ops interface, we can remove all common_* functions.
This allows us to link together the three targets concerned: arm,
hexagon and riscv.

Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
 include/semihosting/common-semi.h   |  7 ------
 target/arm/common-semi-target.c     | 35 -----------------------------
 target/hexagon/common-semi-target.c | 35 -----------------------------
 target/riscv/common-semi-target.c   | 35 -----------------------------
 4 files changed, 112 deletions(-)

diff --git a/include/semihosting/common-semi.h b/include/semihosting/common-semi.h
index f0f8185d8e6..085192e0c86 100644
--- a/include/semihosting/common-semi.h
+++ b/include/semihosting/common-semi.h
@@ -53,12 +53,5 @@ typedef struct SemihostingCPUOps {
 
 void common_semi_cb(CPUState *cs, uint64_t ret, int err);
 void do_common_semihosting(CPUState *cs);
-uint64_t common_semi_arg(CPUState *cs, int argno);
-void common_semi_set_ret(CPUState *cs, uint64_t ret);
-void common_semi_set_err(CPUState *cs, int err);
-bool is_64bit_semihosting(CPUArchState *env);
-bool common_semi_sys_exit_is_extended(CPUState *cs);
-uint64_t common_semi_stack_bottom(CPUState *cs);
-bool common_semi_has_synccache(CPUArchState *env);
 
 #endif /* COMMON_SEMI_H */
diff --git a/target/arm/common-semi-target.c b/target/arm/common-semi-target.c
index dc5f277a59e..ab37730f3ef 100644
--- a/target/arm/common-semi-target.c
+++ b/target/arm/common-semi-target.c
@@ -71,38 +71,3 @@ const SemihostingCPUOps arm_semihosting_ops = {
     .stack_bottom = arm_semi_stack_bottom,
     .has_synccache = arm_semi_has_synccache,
 };
-
-uint64_t common_semi_arg(CPUState *cs, int argno)
-{
-    return arm_semi_arg(cs, argno);
-}
-
-void common_semi_set_ret(CPUState *cs, uint64_t ret)
-{
-    arm_semi_set_ret(cs, ret);
-}
-
-void common_semi_set_err(CPUState *cs, int err)
-{
-    arm_semi_set_err(cs, err);
-}
-
-bool is_64bit_semihosting(CPUArchState *env)
-{
-    return arm_semi_is_64bit(env_cpu(env));
-}
-
-bool common_semi_sys_exit_is_extended(CPUState *cs)
-{
-    return arm_semi_sys_exit_is_extended(cs);
-}
-
-uint64_t common_semi_stack_bottom(CPUState *cs)
-{
-    return arm_semi_stack_bottom(cs);
-}
-
-bool common_semi_has_synccache(CPUArchState *env)
-{
-    return arm_semi_has_synccache(env_cpu(env));
-}
diff --git a/target/hexagon/common-semi-target.c b/target/hexagon/common-semi-target.c
index da92ff298a2..a4c346eff2f 100644
--- a/target/hexagon/common-semi-target.c
+++ b/target/hexagon/common-semi-target.c
@@ -59,38 +59,3 @@ const SemihostingCPUOps hexagon_semihosting_ops = {
     .stack_bottom = hexagon_semi_stack_bottom,
     .has_synccache = hexagon_semi_has_synccache,
 };
-
-uint64_t common_semi_arg(CPUState *cs, int argno)
-{
-    return hexagon_semi_arg(cs, argno);
-}
-
-void common_semi_set_ret(CPUState *cs, uint64_t ret)
-{
-    hexagon_semi_set_ret(cs, ret);
-}
-
-void common_semi_set_err(CPUState *cs, int err)
-{
-    hexagon_semi_set_err(cs, err);
-}
-
-bool is_64bit_semihosting(CPUArchState *env)
-{
-    return hexagon_semi_is_64bit(env_cpu(env));
-}
-
-bool common_semi_sys_exit_is_extended(CPUState *cs)
-{
-    return hexagon_semi_sys_exit_is_extended(cs);
-}
-
-uint64_t common_semi_stack_bottom(CPUState *cs)
-{
-    return hexagon_semi_stack_bottom(cs);
-}
-
-bool common_semi_has_synccache(CPUArchState *env)
-{
-    return hexagon_semi_has_synccache(env_cpu(env));
-}
diff --git a/target/riscv/common-semi-target.c b/target/riscv/common-semi-target.c
index f0f9e29dc4c..44f29a82982 100644
--- a/target/riscv/common-semi-target.c
+++ b/target/riscv/common-semi-target.c
@@ -62,38 +62,3 @@ const SemihostingCPUOps riscv_semihosting_ops = {
     .stack_bottom = riscv_semi_stack_bottom,
     .has_synccache = riscv_semi_has_synccache,
 };
-
-uint64_t common_semi_arg(CPUState *cs, int argno)
-{
-    return riscv_semi_arg(cs, argno);
-}
-
-void common_semi_set_ret(CPUState *cs, uint64_t ret)
-{
-    riscv_semi_set_ret(cs, ret);
-}
-
-void common_semi_set_err(CPUState *cs, int err)
-{
-    riscv_semi_set_err(cs, err);
-}
-
-bool is_64bit_semihosting(CPUArchState *env)
-{
-    return riscv_semi_is_64bit(env_cpu(env));
-}
-
-bool common_semi_sys_exit_is_extended(CPUState *cs)
-{
-    return riscv_semi_sys_exit_is_extended(cs);
-}
-
-uint64_t common_semi_stack_bottom(CPUState *cs)
-{
-    return riscv_semi_stack_bottom(cs);
-}
-
-bool common_semi_has_synccache(CPUArchState *env)
-{
-    return riscv_semi_has_synccache(env_cpu(env));
-}
-- 
2.43.0

[PATCH v3 12/12] meson.build: add hexagon-softmmu to multi-target

[Pierrick Bouvier]

Now that semihosting is solved, hexagon can join the list of target
compatible with others.

Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
 meson.build | 1 +
 1 file changed, 1 insertion(+)

diff --git a/meson.build b/meson.build
index 255c887e8e6..e37ed1687e9 100644
--- a/meson.build
+++ b/meson.build
@@ -4272,6 +4272,7 @@ multi_target_supported_targets = [
   'alpha-softmmu',
   'arm-softmmu',
   'avr-softmmu',
+  'hexagon-softmmu',
   'hppa-softmmu',
   'm68k-softmmu',
   'microblaze-softmmu',
-- 
2.43.0

Re: [PATCH v3 06/12] target/riscv/cpu: constify cpu parameter for riscv_cpu_mxl

[Brian Cain]

[-- Attachment #1: Type: text/plain, Size: 730 bytes --]


On 10/14/2026 4:05 PM, Pierrick Bouvier wrote:
> Signed-off-by: Pierrick Bouvier<pierrick.bouvier@oss.qualcomm.com>
> ---
>   target/riscv/cpu.h | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>



> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 8c8ffe94cd8..00650a66dcb 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -755,7 +755,7 @@ FIELD(EXT_TB_FLAGS, BIG_ENDIAN, 33, 1)
>   #ifdef TARGET_RISCV32
>   #define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
>   #else
> -static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
> +static inline RISCVMXL riscv_cpu_mxl(const CPURISCVState *env)
>   {
>       return env->misa_mxl;
>   }

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Re: [PATCH v3 06/12] target/riscv/cpu: constify cpu parameter for riscv_cpu_mxl

[Philippe Mathieu-Daudé]

On 14/10/26 23:05, Pierrick Bouvier wrote:
> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
> ---
>   target/riscv/cpu.h | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 8c8ffe94cd8..00650a66dcb 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -755,7 +755,7 @@ FIELD(EXT_TB_FLAGS, BIG_ENDIAN, 33, 1)
>   #ifdef TARGET_RISCV32
>   #define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
>   #else
> -static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
> +static inline RISCVMXL riscv_cpu_mxl(const CPURISCVState *env)
>   {
>       return env->misa_mxl;
>   }

Reviewed 6 weeks ago and in Alistair riscv-next queue IIRC:
https://lore.kernel.org/qemu-devel/20260901095229.72018-17-philmd@oss.qualcomm.com/

Anyway,
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>

Re: [PATCH v3 06/12] target/riscv/cpu: constify cpu parameter for riscv_cpu_mxl

[Pierrick Bouvier]

On 10/15/2026 10:37 AM, Philippe Mathieu-Daudé wrote:
> On 14/10/26 23:05, Pierrick Bouvier wrote:
>> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
>> ---
>>   target/riscv/cpu.h | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>> index 8c8ffe94cd8..00650a66dcb 100644
>> --- a/target/riscv/cpu.h
>> +++ b/target/riscv/cpu.h
>> @@ -755,7 +755,7 @@ FIELD(EXT_TB_FLAGS, BIG_ENDIAN, 33, 1)
>>   #ifdef TARGET_RISCV32
>>   #define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
>>   #else
>> -static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
>> +static inline RISCVMXL riscv_cpu_mxl(const CPURISCVState *env)
>>   {
>>       return env->misa_mxl;
>>   }
> 
> Reviewed 6 weeks ago and in Alistair riscv-next queue IIRC:
> https://lore.kernel.org/qemu-devel/20260901095229.72018-17-
> philmd@oss.qualcomm.com/
> 
> Anyway,
> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
> 

Did you flush the rest, or is it going through all submaintainers trees?

I feel that system wide series like this should be sent on their own at
once to avoid having a state spread across multiple people with
different latencies.

Regards,
Pierrick

Re: [PATCH v3 07/12] target/riscv: declare semihosting ops

[Philippe Mathieu-Daudé]

On 14/10/26 23:05, Pierrick Bouvier wrote:
> For now, we keep the global common_* symbols defined.
> 
> Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
> ---
>   target/riscv/common-semi-target.c | 66 ++++++++++++++++++++++++++-----
>   target/riscv/cpu.c                |  4 ++
>   target/riscv/internals.h          |  2 +
>   3 files changed, 62 insertions(+), 10 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>

Re: [PATCH v3 09/12] target/arm: declare semihosting ops

[Philippe Mathieu-Daudé]

On 14/10/26 23:05, Pierrick Bouvier wrote:
> For now, we keep the global common_* symbols defined.
> 
> Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
> ---
>   target/arm/common-semi-target.c | 72 +++++++++++++++++++++++++++------
>   target/arm/cpu.c                |  4 ++
>   target/arm/internals.h          |  2 +
>   3 files changed, 65 insertions(+), 13 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>

Re: [PATCH v3 08/12] target/hexagon: declare semihosting ops

[Philippe Mathieu-Daudé]

On 14/10/26 23:05, Pierrick Bouvier wrote:
> For now, we keep the global common_* symbols defined.
> 
> Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
> ---
>   target/hexagon/common-semi-target.c | 65 ++++++++++++++++++++++++-----
>   target/hexagon/cpu.c                |  2 +
>   target/hexagon/internal.h           |  2 +
>   3 files changed, 59 insertions(+), 10 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>

Re: [PATCH v3 05/12] semihosting: declare semihosting cpu ops

[Philippe Mathieu-Daudé]

On 14/10/26 23:05, Pierrick Bouvier wrote:
> This allows a specific target to declare its implementation of
> semihosting.
> 
> Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
> ---
>   include/hw/core/cpu.h             |  6 ++++++
>   include/semihosting/common-semi.h | 17 +++++++++++++++++
>   2 files changed, 23 insertions(+)

Thanks for addressing the constness changes :)

Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>

Re: [PATCH v3 06/12] target/riscv/cpu: constify cpu parameter for riscv_cpu_mxl

[Philippe Mathieu-Daudé]

On 15/10/26 19:42, Pierrick Bouvier wrote:
> On 10/15/2026 10:37 AM, Philippe Mathieu-Daudé wrote:
>> On 14/10/26 23:05, Pierrick Bouvier wrote:
>>> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
>>> ---
>>>    target/riscv/cpu.h | 2 +-
>>>    1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>>> index 8c8ffe94cd8..00650a66dcb 100644
>>> --- a/target/riscv/cpu.h
>>> +++ b/target/riscv/cpu.h
>>> @@ -755,7 +755,7 @@ FIELD(EXT_TB_FLAGS, BIG_ENDIAN, 33, 1)
>>>    #ifdef TARGET_RISCV32
>>>    #define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
>>>    #else
>>> -static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
>>> +static inline RISCVMXL riscv_cpu_mxl(const CPURISCVState *env)
>>>    {
>>>        return env->misa_mxl;
>>>    }
>>
>> Reviewed 6 weeks ago and in Alistair riscv-next queue IIRC:
>> https://lore.kernel.org/qemu-devel/20260901095229.72018-17-
>> philmd@oss.qualcomm.com/
>>
>> Anyway,
>> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
>>
> 
> Did you flush the rest, or is it going through all submaintainers trees?
> 
> I feel that system wide series like this should be sent on their own at
> once to avoid having a state spread across multiple people with
> different latencies.

No, Alistair queued patches I'm depending on, and I consider a
maintainer sending the "patch queued" message a lock on the
patch. I'm stuck waiting for preliminary riscv-related patches
to get merge to reduce conflict with Alistair tree. Meanwhile
my tree grows so I'm not sure anymore it is a good process,
maybe I should have posted a PR and let Alistair deal with
the rebase conflicts. We still have 10 days until the freeze
so I guess we are still in time.

Re: [PATCH v3 06/12] target/riscv/cpu: constify cpu parameter for riscv_cpu_mxl

[Pierrick Bouvier]

On 10/15/2026 10:48 AM, Philippe Mathieu-Daudé wrote:
> On 15/10/26 19:42, Pierrick Bouvier wrote:
>> On 10/15/2026 10:37 AM, Philippe Mathieu-Daudé wrote:
>>> On 14/10/26 23:05, Pierrick Bouvier wrote:
>>>> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
>>>> ---
>>>>    target/riscv/cpu.h | 2 +-
>>>>    1 file changed, 1 insertion(+), 1 deletion(-)
>>>>
>>>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>>>> index 8c8ffe94cd8..00650a66dcb 100644
>>>> --- a/target/riscv/cpu.h
>>>> +++ b/target/riscv/cpu.h
>>>> @@ -755,7 +755,7 @@ FIELD(EXT_TB_FLAGS, BIG_ENDIAN, 33, 1)
>>>>    #ifdef TARGET_RISCV32
>>>>    #define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
>>>>    #else
>>>> -static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
>>>> +static inline RISCVMXL riscv_cpu_mxl(const CPURISCVState *env)
>>>>    {
>>>>        return env->misa_mxl;
>>>>    }
>>>
>>> Reviewed 6 weeks ago and in Alistair riscv-next queue IIRC:
>>> https://lore.kernel.org/qemu-devel/20260901095229.72018-17-
>>> philmd@oss.qualcomm.com/
>>>
>>> Anyway,
>>> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
>>>
>>
>> Did you flush the rest, or is it going through all submaintainers trees?
>>
>> I feel that system wide series like this should be sent on their own at
>> once to avoid having a state spread across multiple people with
>> different latencies.
> 
> No, Alistair queued patches I'm depending on, and I consider a
> maintainer sending the "patch queued" message a lock on the
> patch. I'm stuck waiting for preliminary riscv-related patches
> to get merge to reduce conflict with Alistair tree. Meanwhile
> my tree grows so I'm not sure anymore it is a good process,
> maybe I should have posted a PR and let Alistair deal with
> the rebase conflicts. We still have 10 days until the freeze
> so I guess we are still in time.

As long as the patch is strictly unmodified, the sub maintainer or top
maintainer (merging the PR) won't see a conflict, since it's all done
using git, and not email patches.

In case there is a conflict, I would say it's definitely a
submaintainer's problem since their tree is the one with a local state
fixing conflicts between multiple series: probably a strong hint it
should have been flushed quicker.
As long as they don't have to deal with conflict, by keeping an
invisible "lock" on this subtree, there is no reason for the workflow to
change.

I understand your situation though, there is no good way to deal with a
series that depends on another in flight series: either avoid this, or
repeat the required patches in your own.

Regards,
Pierrick

Re: [PATCH v3 06/12] target/riscv/cpu: constify cpu parameter for riscv_cpu_mxl

[Philippe Mathieu-Daudé]

On 15/10/26 20:09, Pierrick Bouvier wrote:
> On 10/15/2026 10:48 AM, Philippe Mathieu-Daudé wrote:
>> On 15/10/26 19:42, Pierrick Bouvier wrote:
>>> On 10/15/2026 10:37 AM, Philippe Mathieu-Daudé wrote:
>>>> On 14/10/26 23:05, Pierrick Bouvier wrote:
>>>>> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
>>>>> ---
>>>>>     target/riscv/cpu.h | 2 +-
>>>>>     1 file changed, 1 insertion(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>>>>> index 8c8ffe94cd8..00650a66dcb 100644
>>>>> --- a/target/riscv/cpu.h
>>>>> +++ b/target/riscv/cpu.h
>>>>> @@ -755,7 +755,7 @@ FIELD(EXT_TB_FLAGS, BIG_ENDIAN, 33, 1)
>>>>>     #ifdef TARGET_RISCV32
>>>>>     #define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
>>>>>     #else
>>>>> -static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
>>>>> +static inline RISCVMXL riscv_cpu_mxl(const CPURISCVState *env)
>>>>>     {
>>>>>         return env->misa_mxl;
>>>>>     }
>>>>
>>>> Reviewed 6 weeks ago and in Alistair riscv-next queue IIRC:
>>>> https://lore.kernel.org/qemu-devel/20260901095229.72018-17-
>>>> philmd@oss.qualcomm.com/
>>>>
>>>> Anyway,
>>>> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
>>>>
>>>
>>> Did you flush the rest, or is it going through all submaintainers trees?
>>>
>>> I feel that system wide series like this should be sent on their own at
>>> once to avoid having a state spread across multiple people with
>>> different latencies.
>>
>> No, Alistair queued patches I'm depending on, and I consider a
>> maintainer sending the "patch queued" message a lock on the
>> patch. I'm stuck waiting for preliminary riscv-related patches
>> to get merge to reduce conflict with Alistair tree. Meanwhile
>> my tree grows so I'm not sure anymore it is a good process,
>> maybe I should have posted a PR and let Alistair deal with
>> the rebase conflicts. We still have 10 days until the freeze
>> so I guess we are still in time.
> 
> As long as the patch is strictly unmodified, the sub maintainer or top
> maintainer (merging the PR) won't see a conflict, since it's all done
> using git, and not email patches.

Fundamentals of git indeed. I'll try, hoping that improve the pace we
get series merge, hoping it won't disturb Alistair tree.
> In case there is a conflict, I would say it's definitely a
> submaintainer's problem since their tree is the one with a local state
> fixing conflicts between multiple series: probably a strong hint it
> should have been flushed quicker.
> As long as they don't have to deal with conflict, by keeping an
> invisible "lock" on this subtree, there is no reason for the workflow to
> change.
> 
> I understand your situation though, there is no good way to deal with a
> series that depends on another in flight series: either avoid this, or
> repeat the required patches in your own.
> 
> Regards,
> Pierrick
>