[PATCH 0/2] Minor fixes and improvements for Virtual IRQs

[PATCH 0/2] Minor fixes and improvements for Virtual IRQs

[Rajnesh Kanwal]

This series contains few miscellaneous fixes related to Virtual IRQs
and related code. The first patch changes CSR mask widths to 64bit
as AIA introduces half CSRs in case of 32bit systems.

Second patch fixes guest and core local IRQ overlap. Qemu creates
a single IRQ range which is shared between core local interrupts
and guests in riscv_cpu_init(). Even though, in the current state
there is no device generating interrupts in the 13:63 range, and
virtual IRQ logic in Qemu also doesn't go through riscv_cpu_set_irq()
path, it's better to keep local and guest range separate to avoid
confusion and any future issues.

Patches can be found here on github:
https://github.com/rajnesh-kanwal/qemu/tree/dev/rkanwal/irq_fixes

Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
---
Rajnesh Kanwal (2):
  target/riscv: Extend virtual irq csrs masks to be 64 bit wide.
  target/riscv: Move Guest irqs out of the core local irqs range.

 target/riscv/cpu_bits.h |  3 ++-
 target/riscv/csr.c      | 21 +++++++++++++--------
 2 files changed, 15 insertions(+), 9 deletions(-)
---
base-commit: 09d8c49f23e9a130593984d5c8cf048bdd76f73e
-- 
Regards,
Rajnesh Kanwal

[PATCH 1/2] target/riscv: Extend virtual irq csrs masks to be 64 bit wide.

[Rajnesh Kanwal]

AIA extends the width of all IRQ CSRs to 64bit even
in 32bit systems by adding missing half CSRs.

This seems to be missed while adding support for
virtual IRQs. The whole logic seems to be correct
except the width of the masks.

Fixes: 1697837ed9 ("target/riscv: Add M-mode virtual
interrupt and IRQ filtering support.")
Fixes: 40336d5b1d ("target/riscv: Add HS-mode virtual
interrupt and IRQ filtering support.")

Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
---
 target/riscv/csr.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 45b548eb0b..c9d685dcc5 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1193,18 +1193,18 @@ static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
  */
 
 /* Bit STIP can be an alias of mip.STIP that's why it's writable in mvip. */
-static const target_ulong mvip_writable_mask = MIP_SSIP | MIP_STIP | MIP_SEIP |
+static const uint64_t mvip_writable_mask = MIP_SSIP | MIP_STIP | MIP_SEIP |
                                     LOCAL_INTERRUPTS;
-static const target_ulong mvien_writable_mask = MIP_SSIP | MIP_SEIP |
+static const uint64_t mvien_writable_mask = MIP_SSIP | MIP_SEIP |
                                     LOCAL_INTERRUPTS;
 
-static const target_ulong sip_writable_mask = SIP_SSIP | LOCAL_INTERRUPTS;
-static const target_ulong hip_writable_mask = MIP_VSSIP;
-static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP |
+static const uint64_t sip_writable_mask = SIP_SSIP | LOCAL_INTERRUPTS;
+static const uint64_t hip_writable_mask = MIP_VSSIP;
+static const uint64_t hvip_writable_mask = MIP_VSSIP | MIP_VSTIP |
                                     MIP_VSEIP | LOCAL_INTERRUPTS;
-static const target_ulong hvien_writable_mask = LOCAL_INTERRUPTS;
+static const uint64_t hvien_writable_mask = LOCAL_INTERRUPTS;
 
-static const target_ulong vsip_writable_mask = MIP_VSSIP | LOCAL_INTERRUPTS;
+static const uint64_t vsip_writable_mask = MIP_VSSIP | LOCAL_INTERRUPTS;
 
 const bool valid_vm_1_10_32[16] = {
     [VM_1_10_MBARE] = true,
-- 
2.34.1

[PATCH 2/2] target/riscv: Move Guest irqs out of the core local irqs range.

[Rajnesh Kanwal]

Qemu maps IRQs 0:15 for core interrupts and 16 onward for
guest interrupts which are later translated to hgiep in
`riscv_cpu_set_irq()` function.

With virtual IRQ support added, software now can fully
use the whole local interrupt range without any actual
hardware attached.

This change moves the guest interrupt range after the
core local interrupt range to avoid clash.

Fixes: 1697837ed9 ("target/riscv: Add M-mode virtual
interrupt and IRQ filtering support.")
Fixes: 40336d5b1d ("target/riscv: Add HS-mode virtual
interrupt and IRQ filtering support.")

Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
---
 target/riscv/cpu_bits.h | 3 ++-
 target/riscv/csr.c      | 7 ++++++-
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 13ce2218d1..33f28bb115 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -664,7 +664,8 @@ typedef enum RISCVException {
 #define IRQ_M_EXT                          11
 #define IRQ_S_GEXT                         12
 #define IRQ_PMU_OVF                        13
-#define IRQ_LOCAL_MAX                      16
+#define IRQ_LOCAL_MAX                      64
+/* -1 is due to bit zero of hgeip and hgeie being ROZ. */
 #define IRQ_LOCAL_GUEST_MAX                (TARGET_LONG_BITS - 1)
 
 /* mip masks */
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index c9d685dcc5..78f42fcae5 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1141,7 +1141,12 @@ static RISCVException write_stimecmph(CPURISCVState *env, int csrno,
 
 #define VSTOPI_NUM_SRCS 5
 
-#define LOCAL_INTERRUPTS (~0x1FFF)
+/* All core local interrupts except the fixed ones 0:12. This macro is for virtual
+ * interrupts logic so please don't change this to avoid messing up the whole support,
+ * For reference see AIA spec: `5.3 Interrupt filtering and virtual interrupts for
+ * supervisor level` and `6.3.2 Virtual interrupts for VS level`.
+ */
+#define LOCAL_INTERRUPTS   (~0x1FFFULL)
 
 static const uint64_t delegable_ints =
     S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS | MIP_LCOFIP;
-- 
2.34.1

Re: [PATCH 1/2] target/riscv: Extend virtual irq csrs masks to be 64 bit wide.

[Daniel Henrique Barboza]

On 5/13/24 08:46, Rajnesh Kanwal wrote:
> AIA extends the width of all IRQ CSRs to 64bit even
> in 32bit systems by adding missing half CSRs.
> 
> This seems to be missed while adding support for
> virtual IRQs. The whole logic seems to be correct
> except the width of the masks.
> 
> Fixes: 1697837ed9 ("target/riscv: Add M-mode virtual
> interrupt and IRQ filtering support.")
> Fixes: 40336d5b1d ("target/riscv: Add HS-mode virtual
> interrupt and IRQ filtering support.")
> 

Please avoid splitting the commit title when including them in a "Fixes"
tag. It is ok if the commit this breaks the usual char limit:

> Fixes: 1697837ed9 ("target/riscv: Add M-mode virtual interrupt and IRQ filtering support.")
> Fixes: 40336d5b1d ("target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.")


As for the code:


Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

> Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
> ---
>   target/riscv/csr.c | 14 +++++++-------
>   1 file changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 45b548eb0b..c9d685dcc5 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1193,18 +1193,18 @@ static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
>    */
>   
>   /* Bit STIP can be an alias of mip.STIP that's why it's writable in mvip. */
> -static const target_ulong mvip_writable_mask = MIP_SSIP | MIP_STIP | MIP_SEIP |
> +static const uint64_t mvip_writable_mask = MIP_SSIP | MIP_STIP | MIP_SEIP |
>                                       LOCAL_INTERRUPTS;
> -static const target_ulong mvien_writable_mask = MIP_SSIP | MIP_SEIP |
> +static const uint64_t mvien_writable_mask = MIP_SSIP | MIP_SEIP |
>                                       LOCAL_INTERRUPTS;
>   
> -static const target_ulong sip_writable_mask = SIP_SSIP | LOCAL_INTERRUPTS;
> -static const target_ulong hip_writable_mask = MIP_VSSIP;
> -static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP |
> +static const uint64_t sip_writable_mask = SIP_SSIP | LOCAL_INTERRUPTS;
> +static const uint64_t hip_writable_mask = MIP_VSSIP;
> +static const uint64_t hvip_writable_mask = MIP_VSSIP | MIP_VSTIP |
>                                       MIP_VSEIP | LOCAL_INTERRUPTS;
> -static const target_ulong hvien_writable_mask = LOCAL_INTERRUPTS;
> +static const uint64_t hvien_writable_mask = LOCAL_INTERRUPTS;
>   
> -static const target_ulong vsip_writable_mask = MIP_VSSIP | LOCAL_INTERRUPTS;
> +static const uint64_t vsip_writable_mask = MIP_VSSIP | LOCAL_INTERRUPTS;
>   
>   const bool valid_vm_1_10_32[16] = {
>       [VM_1_10_MBARE] = true,

Re: [PATCH 2/2] target/riscv: Move Guest irqs out of the core local irqs range.

[Daniel Henrique Barboza]

On 5/13/24 08:46, Rajnesh Kanwal wrote:
> Qemu maps IRQs 0:15 for core interrupts and 16 onward for
> guest interrupts which are later translated to hgiep in
> `riscv_cpu_set_irq()` function.
> 
> With virtual IRQ support added, software now can fully
> use the whole local interrupt range without any actual
> hardware attached.
> 
> This change moves the guest interrupt range after the
> core local interrupt range to avoid clash.
> 
> Fixes: 1697837ed9 ("target/riscv: Add M-mode virtual
> interrupt and IRQ filtering support.")
> Fixes: 40336d5b1d ("target/riscv: Add HS-mode virtual
> interrupt and IRQ filtering support.")
> 

As I said in patch 1, please do not split the commit titles in a
"Fixes" tag:

> Fixes: 1697837ed9 ("target/riscv: Add M-mode virtual interrupt and IRQ filtering support.")
> Fixes: 40336d5b1d ("target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.")


> Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
> ---
>   target/riscv/cpu_bits.h | 3 ++-
>   target/riscv/csr.c      | 7 ++++++-
>   2 files changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 13ce2218d1..33f28bb115 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -664,7 +664,8 @@ typedef enum RISCVException {
>   #define IRQ_M_EXT                          11
>   #define IRQ_S_GEXT                         12
>   #define IRQ_PMU_OVF                        13
> -#define IRQ_LOCAL_MAX                      16
> +#define IRQ_LOCAL_MAX                      64
> +/* -1 is due to bit zero of hgeip and hgeie being ROZ. */
>   #define IRQ_LOCAL_GUEST_MAX                (TARGET_LONG_BITS - 1)
>   
>   /* mip masks */
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index c9d685dcc5..78f42fcae5 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1141,7 +1141,12 @@ static RISCVException write_stimecmph(CPURISCVState *env, int csrno,
>   
>   #define VSTOPI_NUM_SRCS 5
>   
> -#define LOCAL_INTERRUPTS (~0x1FFF)
> +/* All core local interrupts except the fixed ones 0:12. This macro is for virtual
> + * interrupts logic so please don't change this to avoid messing up the whole support,
> + * For reference see AIA spec: `5.3 Interrupt filtering and virtual interrupts for
> + * supervisor level` and `6.3.2 Virtual interrupts for VS level`.
> + */

The comment format we use is capped at 80 chars per line and starts with a
leading /*  on a separated line:


> +/*
> +/* All core local interrupts except the fixed ones 0:12. This macro is
> +/* for virtual interrupts logic so please don't change this to avoid
> +/* messing up the whole support. For reference see AIA spec:
> +/* `5.3 Interrupt filtering and virtual interrupts for supervisor level`
> +/* and `6.3.2 Virtual interrupts for VS level`.
> + */

You can run ./scripts/checkpatch.pl in the generated patch file to see if the
patch is compliant with the expected code style.



Thanks,


Daniel



> +#define LOCAL_INTERRUPTS   (~0x1FFFULL)
>   
>   static const uint64_t delegable_ints =
>       S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS | MIP_LCOFIP;