From: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
To: u-boot@lists.denx.de
Subject: [PATCH v4 14/21] arch: arm: socfpga: Add 'altr, sysmgr-syscon' for MMC node in device tree
Date: Tue, 10 Mar 2020 18:05:33 +0100 [thread overview]
Message-ID: <a2f6eca9-fba3-7937-d4ab-86f7cc8ea87f@gmail.com> (raw)
In-Reply-To: <1583744842-24632-15-git-send-email-chee.hong.ang@intel.com>
Am 09.03.2020 um 10:07 schrieb chee.hong.ang at intel.com:
> From: Chee Hong Ang <chee.hong.ang@intel.com>
>
> In device tree for all socfpga platforms, a phandle to System Manager
> ('altr,sysmgr-syscon') is needed for MMC node to enable the MMC driver
> to configure the SDMMC's clock phase shift via System Manager driver
> (altera_sysmgr).
> This phandle specifies the offset of the SDMCC control register in
> System Manager, start of bit field for drvsel and start of bit field
> for smplsel.
>
> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
> ---
> arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 1 +
> arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 1 +
> arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi | 1 +
> arch/arm/dts/socfpga_cyclone5.dtsi | 1 +
> arch/arm/dts/socfpga_stratix10.dtsi | 1 -
> arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 7 +++++++
> arch/arm/dts/socfpga_stratix10_socdk.dts | 2 --
This looks strange. I would have expected you add the 'syscon' entry to
the base dtsi files (and to the ones in Linux, too, btw). But you're
adding it to "-u-boot.dtsi" files, too. Why?
Regards,
Simon
> 7 files changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
> index 1908be4..56fd7d9 100644
> --- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
> +++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
> @@ -34,6 +34,7 @@
> &mmc {
> drvsel = <3>;
> smplsel = <0>;
> + altr,sysmgr-syscon = <&sysmgr 0x28 0 4>;
> u-boot,dm-pre-reloc;
> };
>
> diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> index d6b6c2d..887673b 100644
> --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> @@ -44,6 +44,7 @@
> cap-sd-highspeed;
> broken-cd;
> bus-width = <4>;
> + altr,sysmgr-syscon = <&sysmgr 0x28 0 4>;
> };
>
> &eccmgr {
> diff --git a/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi
> index dfaff4c..d2189f1 100644
> --- a/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi
> +++ b/arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi
> @@ -20,6 +20,7 @@
> };
>
> &mmc {
> + altr,sysmgr-syscon = <&sysmgr 0x108 0 3>;
> u-boot,dm-pre-reloc;
> };
>
> diff --git a/arch/arm/dts/socfpga_cyclone5.dtsi b/arch/arm/dts/socfpga_cyclone5.dtsi
> index 319a71e..c309681 100644
> --- a/arch/arm/dts/socfpga_cyclone5.dtsi
> +++ b/arch/arm/dts/socfpga_cyclone5.dtsi
> @@ -23,6 +23,7 @@
> bus-width = <4>;
> cap-mmc-highspeed;
> cap-sd-highspeed;
> + altr,sysmgr-syscon = <&sysmgr 0x108 0 3>;
> };
>
> sysmgr at ffd08000 {
> diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi
> index a8e61cf..9c89065 100755
> --- a/arch/arm/dts/socfpga_stratix10.dtsi
> +++ b/arch/arm/dts/socfpga_stratix10.dtsi
> @@ -228,7 +228,6 @@
> interrupts = <0 96 4>;
> fifo-depth = <0x400>;
> resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
> - u-boot,dm-pre-reloc;
> status = "disabled";
> };
>
> diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
> index a903040..ca91b40 100755
> --- a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
> +++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
> @@ -28,6 +28,13 @@
> u-boot,dm-pre-reloc;
> };
>
> +&mmc {
> + drvsel = <3>;
> + smplsel = <0>;
> + altr,sysmgr-syscon = <&sysmgr 0x28 0 4>;
> + u-boot,dm-pre-reloc;
> +};
> +
> &sysmgr {
> u-boot,dm-pre-reloc;
> };
> diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts
> index b7b48a5..ff6e1b2 100755
> --- a/arch/arm/dts/socfpga_stratix10_socdk.dts
> +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts
> @@ -91,8 +91,6 @@
> cap-mmc-highspeed;
> broken-cd;
> bus-width = <4>;
> - drvsel = <3>;
> - smplsel = <0>;
> };
>
> &qspi {
>
next prev parent reply other threads:[~2020-03-10 17:05 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-09 9:07 [PATCH v4 00/21] Enable ARM Trusted Firmware for U-Boot chee.hong.ang at intel.com
2020-03-09 9:07 ` [PATCH v4 01/21] configs: agilex: Remove CONFIG_OF_EMBED chee.hong.ang at intel.com
2020-03-09 9:07 ` [PATCH v4 02/21] arm: socfpga: add fit source file for pack itb with ATF chee.hong.ang at intel.com
2020-03-09 9:07 ` [PATCH v4 03/21] arm: socfpga: Add function for checking description from FIT image chee.hong.ang at intel.com
2020-03-09 9:07 ` [PATCH v4 04/21] arm: socfpga: Load FIT image with ATF support chee.hong.ang at intel.com
2020-03-09 9:07 ` [PATCH v4 05/21] arm: socfpga: Override 'lowlevel_init' to support ATF chee.hong.ang at intel.com
2020-03-09 9:07 ` [PATCH v4 06/21] configs: socfpga: Enable FIT image loading with ATF support chee.hong.ang at intel.com
2020-03-09 9:07 ` [PATCH v4 07/21] arm: socfpga: Disable "spin-table" method for booting Linux chee.hong.ang at intel.com
2020-03-09 9:07 ` [PATCH v4 08/21] arm: socfpga: Add SMC helper function for Intel SOCFPGA (64bits) chee.hong.ang at intel.com
2020-03-09 9:07 ` [PATCH v4 09/21] arm: socfpga: Define SMC function identifiers for PSCI SiP services chee.hong.ang at intel.com
2020-03-09 9:07 ` [PATCH v4 10/21] arm: socfpga: soc64: Remove PHY interface setup from misc arch init chee.hong.ang at intel.com
2020-03-09 9:07 ` [PATCH v4 11/21] misc: altera_sysmgr: Add Altera System Manager driver chee.hong.ang at intel.com
2020-03-10 16:17 ` Simon Goldschmidt
2020-03-10 16:42 ` Ang, Chee Hong
2020-03-10 16:57 ` Simon Goldschmidt
2020-03-10 20:14 ` Simon Goldschmidt
2020-03-11 6:35 ` Ang, Chee Hong
2020-03-11 6:37 ` Marek Vasut
2020-03-11 7:03 ` Ang, Chee Hong
2020-03-11 7:06 ` Marek Vasut
2020-03-11 8:13 ` Ang, Chee Hong
2020-03-09 9:07 ` [PATCH v4 12/21] arch: arm: socfpga: Enable driver model for misc drivers chee.hong.ang at intel.com
2020-03-10 17:03 ` Simon Goldschmidt
2020-03-11 6:13 ` Ang, Chee Hong
2020-03-09 9:07 ` [PATCH v4 13/21] mmc: dwmmc: socfpga: MMC driver access System Manager via 'altera_sysmgr' chee.hong.ang at intel.com
2020-03-09 9:07 ` [PATCH v4 14/21] arch: arm: socfpga: Add 'altr, sysmgr-syscon' for MMC node in device tree chee.hong.ang at intel.com
2020-03-10 17:05 ` Simon Goldschmidt [this message]
2020-03-11 7:06 ` Ang, Chee Hong
2020-03-11 7:14 ` Marek Vasut
2020-03-09 9:07 ` [PATCH v4 15/21] net: designware: socfpga: MAC driver access System Manager via 'altera_sysmgr' chee.hong.ang at intel.com
2020-03-09 9:07 ` [PATCH v4 16/21] arm: socfpga: Add ATF support for Reset Manager driver chee.hong.ang at intel.com
2020-03-09 9:07 ` [PATCH v4 17/21] arm: socfpga: stratix10: Initialize timer in SPL chee.hong.ang at intel.com
2020-03-09 9:07 ` [PATCH v4 18/21] arm: socfpga: Add ATF support to query FPGA configuration status chee.hong.ang at intel.com
2020-03-09 9:07 ` [PATCH v4 19/21] arm: socfpga: stratix10: Add ATF support for FPGA reconfig driver chee.hong.ang at intel.com
2020-03-09 9:07 ` [PATCH v4 20/21] arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to mbox_reset_cold() chee.hong.ang at intel.com
2020-03-09 9:07 ` [PATCH v4 21/21] configs: socfpga: Add defconfig for Agilex and Stratix 10 without ATF support chee.hong.ang at intel.com
2020-03-10 17:01 ` [PATCH v4 00/21] Enable ARM Trusted Firmware for U-Boot Simon Goldschmidt
2020-03-11 6:11 ` Ang, Chee Hong
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=a2f6eca9-fba3-7937-d4ab-86f7cc8ea87f@gmail.com \
--to=simon.k.r.goldschmidt@gmail.com \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.