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From: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
To: Cezary Rojewski <cezary.rojewski@intel.com>, alsa-devel@alsa-project.org
Cc: upstream@semihalf.com, harshapriya.n@intel.com, rad@semihalf.com,
	tiwai@suse.com, hdegoede@redhat.com, broonie@kernel.org,
	amadeuszx.slawinski@linux.intel.com, cujomalainey@chromium.org,
	lma@semihalf.com
Subject: Re: [RFC 04/13] ASoC: Intel: avs: Parse pplcfg and binding tuples
Date: Fri, 25 Feb 2022 11:40:19 -0600	[thread overview]
Message-ID: <a32be4cf-3d33-4ffe-71ce-84cd500d520f@linux.intel.com> (raw)
In-Reply-To: <20220207132532.3782412-5-cezary.rojewski@intel.com>



On 2/7/22 07:25, Cezary Rojewski wrote:
> Stream on ADSP firmware is represented by one or more pipelines. Just

I have a lot of questions on this one line...

what is a 'stream'?

'stream' historically means 'direction' in ALSA.

Then we have sdw_stream, which describes how source and sink ports are
connected on a platform.

We also have DPCM front-ends, visible mostly through the PCM device they
expose to users.

In windows we have stream effects that are really meant to be on a
single dedicated pipeline.

other questions: can a stream represent data moving in different
directions, e.g. in full-duplex mode.

How would a loopback be described?

What happens when a data path is split (demux) or merged (mixer)?

How is a 'stream' different from a 'path template' that you referred to
in Patch RFC 02/13

You would need at least 10 lines of plain English to make sure no one
will misunderstand what 'stream' means.

> like modules, these are described by a config structure. Add parsing
> helpers to support loading such information from the topology file.
>
> +/* Specifies path behaviour during PCM ->trigger(START) commnand. */

typo: command.

> +enum avs_tplg_trigger {
> +	AVS_TPLG_TRIGGER_AUTO = 0,
> +	AVS_TPLG_TRIGGER_USERSPACE = 1, /* via sysfs */

The feedback in previous versions was that we should not expose any
sysfs interface that would interfere with decisions made by the driver.

This is very controversial and a major hurdle to upstream any of this.

Debugfs is fine, as suggested by Mark as well

"
If it's mainly used for debugging then it could be exposed through
debugfs with less worry.
"


> +};
> +
> +struct avs_tplg_pplcfg {
> +	u16 req_size;

what does this describe?

> +	u8 priority;
> +	bool lp;
> +	u16 attributes;
> +	enum avs_tplg_trigger trigger;
> +};
> +
> +struct avs_tplg_binding {
> +	char target_tplg_name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
> +	u32 target_path_tmpl_id;
> +	u32 target_ppl_id;
> +	u32 target_mod_id;
> +	u8 target_mod_pin;

you really need to elaborate on what a template is, and how you use a
template and a ppl id concurrently.

> +	u32 mod_id;
> +	u8 mod_pin;
> +	u8 is_sink;
> +};
> +
>  #endif

  reply	other threads:[~2022-02-25 20:56 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-07 13:25 [RFC 00/13] ASoC: Intel: avs: Topology and path management Cezary Rojewski
2022-02-07 13:25 ` [RFC 01/13] ASoC: Intel: avs: Declare vendor tokens Cezary Rojewski
2022-02-07 13:25 ` [RFC 02/13] ASoC: Intel: avs: Add topology parsing infrastructure Cezary Rojewski
2022-02-25 17:20   ` Pierre-Louis Bossart
2022-03-21 10:25     ` Cezary Rojewski
2022-02-07 13:25 ` [RFC 03/13] ASoC: Intel: avs: Parse module-extension tuples Cezary Rojewski
2022-02-25 17:24   ` Pierre-Louis Bossart
2022-03-21 10:33     ` Cezary Rojewski
2022-02-07 13:25 ` [RFC 04/13] ASoC: Intel: avs: Parse pplcfg and binding tuples Cezary Rojewski
2022-02-25 17:40   ` Pierre-Louis Bossart [this message]
2022-03-21 10:53     ` Cezary Rojewski
2022-02-07 13:25 ` [RFC 05/13] ASoC: Intel: avs: Parse pipeline and module tuples Cezary Rojewski
2022-02-25 18:51   ` Pierre-Louis Bossart
2022-03-21 15:14     ` Cezary Rojewski
2022-02-07 13:25 ` [RFC 06/13] ASoC: Intel: avs: Parse path and path templates tuples Cezary Rojewski
2022-02-25 19:09   ` Pierre-Louis Bossart
2022-03-21 16:15     ` Cezary Rojewski
2022-02-07 13:25 ` [RFC 07/13] ASoC: Intel: avs: Add topology loading operations Cezary Rojewski
2022-02-25 19:17   ` Pierre-Louis Bossart
2022-03-21 16:28     ` Cezary Rojewski
2022-02-07 13:25 ` [RFC 08/13] ASoC: Intel: avs: Declare path and its components Cezary Rojewski
2022-02-25 19:25   ` Pierre-Louis Bossart
2022-03-21 17:01     ` Cezary Rojewski
2022-03-21 18:14       ` Pierre-Louis Bossart
2022-02-07 13:25 ` [RFC 09/13] ASoC: Intel: avs: Path creation and freeing Cezary Rojewski
2022-02-25 19:36   ` Pierre-Louis Bossart
2022-03-21 17:19     ` Cezary Rojewski
2022-03-21 17:53       ` Cezary Rojewski
2022-02-07 13:25 ` [RFC 10/13] ASoC: Intel: avs: Path state management Cezary Rojewski
2022-02-25 19:42   ` Pierre-Louis Bossart
2022-03-21 17:31     ` Cezary Rojewski
2022-02-07 13:25 ` [RFC 11/13] ASoC: Intel: avs: Arm paths after creating them Cezary Rojewski
2022-02-07 13:25 ` [RFC 12/13] ASoC: Intel: avs: Prepare modules before bindings them Cezary Rojewski
2022-02-07 13:25 ` [RFC 13/13] ASoC: Intel: avs: Configure modules according to their type Cezary Rojewski
2022-02-25 21:35 ` [RFC 00/13] ASoC: Intel: avs: Topology and path management Pierre-Louis Bossart
2022-02-26  0:22   ` Mark Brown

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