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From: Sean Anderson <sean.anderson@linux.dev>
To: Rob Herring <robh@kernel.org>
Cc: "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	linux-pci@vger.kernel.org, "Michal Simek" <michal.simek@amd.com>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Thippeswamy Havalige" <thippeswamy.havalige@amd.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	devicetree@vger.kernel.org
Subject: Re: [PATCH v2 1/7] dt-bindings: pci: xilinx-nwl: Add phys
Date: Tue, 7 May 2024 16:07:18 -0400	[thread overview]
Message-ID: <a4347e43-06f7-4ede-b50f-554d1194a1f6@linux.dev> (raw)
In-Reply-To: <20240507200640.GA955773-robh@kernel.org>

On 5/7/24 16:06, Rob Herring wrote:
> On Mon, May 06, 2024 at 12:15:04PM -0400, Sean Anderson wrote:
>> Add phys properties so Linux can power-on/configure the GTR
>> transcievers.
>> 
>> Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
>> ---
>> 
>> Changes in v2:
>> - Remove phy-names
>> - Add an example
>> 
>>  Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 6 ++++++
>>  1 file changed, 6 insertions(+)
>> 
>> diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
>> index 426f90a47f35..693b29039a9b 100644
>> --- a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
>> +++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
>> @@ -61,6 +61,10 @@ properties:
>>    interrupt-map:
>>      maxItems: 4
>>  
>> +  phys:
>> +    minItems: 1
>> +    maxItems: 4
> 
> I assume this is 1 phy per lane, but don't make me assume and define it.
> 
> Rob

It's one per lane. I'll add that to the description.

--Sean

WARNING: multiple messages have this Message-ID (diff)
From: Sean Anderson <sean.anderson@linux.dev>
To: Rob Herring <robh@kernel.org>
Cc: "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	linux-pci@vger.kernel.org, "Michal Simek" <michal.simek@amd.com>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Thippeswamy Havalige" <thippeswamy.havalige@amd.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	devicetree@vger.kernel.org
Subject: Re: [PATCH v2 1/7] dt-bindings: pci: xilinx-nwl: Add phys
Date: Tue, 7 May 2024 16:07:18 -0400	[thread overview]
Message-ID: <a4347e43-06f7-4ede-b50f-554d1194a1f6@linux.dev> (raw)
In-Reply-To: <20240507200640.GA955773-robh@kernel.org>

On 5/7/24 16:06, Rob Herring wrote:
> On Mon, May 06, 2024 at 12:15:04PM -0400, Sean Anderson wrote:
>> Add phys properties so Linux can power-on/configure the GTR
>> transcievers.
>> 
>> Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
>> ---
>> 
>> Changes in v2:
>> - Remove phy-names
>> - Add an example
>> 
>>  Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 6 ++++++
>>  1 file changed, 6 insertions(+)
>> 
>> diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
>> index 426f90a47f35..693b29039a9b 100644
>> --- a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
>> +++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
>> @@ -61,6 +61,10 @@ properties:
>>    interrupt-map:
>>      maxItems: 4
>>  
>> +  phys:
>> +    minItems: 1
>> +    maxItems: 4
> 
> I assume this is 1 phy per lane, but don't make me assume and define it.
> 
> Rob

It's one per lane. I'll add that to the description.

--Sean

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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2024-05-07 20:07 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-05-06 16:15 [PATCH v2 0/7] PCI: xilinx-nwl: Add phy support Sean Anderson
2024-05-06 16:15 ` Sean Anderson
2024-05-06 16:15 ` [PATCH v2 1/7] dt-bindings: pci: xilinx-nwl: Add phys Sean Anderson
2024-05-06 16:15   ` Sean Anderson
2024-05-07 20:06   ` Rob Herring
2024-05-07 20:06     ` Rob Herring
2024-05-07 20:07     ` Sean Anderson [this message]
2024-05-07 20:07       ` Sean Anderson
2024-05-06 16:15 ` [PATCH v2 2/7] PCI: xilinx-nwl: Fix off-by-one Sean Anderson
2024-05-06 16:15   ` Sean Anderson
2024-05-08  1:59   ` Bjorn Helgaas
2024-05-08  1:59     ` Bjorn Helgaas
2024-05-09 21:34     ` Sean Anderson
2024-05-09 21:34       ` Sean Anderson
2024-05-06 16:15 ` [PATCH v2 3/7] PCI: xilinx-nwl: Fix register misspelling Sean Anderson
2024-05-06 16:15   ` Sean Anderson
2024-05-06 16:15 ` [PATCH v2 4/7] PCI: xilinx-nwl: Rate-limit misc interrupt messages Sean Anderson
2024-05-06 16:15   ` Sean Anderson
2024-05-06 16:15 ` [PATCH v2 5/7] PCI: xilinx-nwl: Clean up clock on probe failure/removal Sean Anderson
2024-05-06 16:15   ` Sean Anderson
2024-05-06 16:15 ` [PATCH v2 6/7] PCI: xilinx-nwl: Add phy support Sean Anderson
2024-05-06 16:15   ` Sean Anderson
2024-05-06 16:15 ` [PATCH v2 7/7] arm64: zynqmp: Add PCIe phys Sean Anderson
2024-05-06 16:15   ` Sean Anderson

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