diff for duplicates of <a8c3391d-7109-47bf-e1c4-9217fc68bfd0@codeaurora.org> diff --git a/a/1.txt b/N1/1.txt index e94ee0f..e4c903d 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -12,8 +12,8 @@ On 4/17/2018 6:53 PM, John David Anglin wrote: >> writel() of PA-RISC needs to ensure that 3. cannot bypass 1. This is typically >> done by a write barrier embedded into the writel() on relaxed architectures. > The sequence point after the argument evaluation for writel prevents the compiler from reordering -> 1 and 2. Accesses to I/O space are strongly ordered on PA-RISC, so 1 must occur before 2 (Page G-1 -> of the PA-RISC 2.0 Architecture). Thus, the current code is okay. +> 1 and 2.? Accesses to I/O space are strongly ordered on PA-RISC, so 1 must occur before 2 (Page G-1 +> of the PA-RISC 2.0 Architecture).? Thus, the current code is okay. > Many thanks for the clarification. diff --git a/a/content_digest b/N1/content_digest index b6ed4fe..2fc93a1 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -5,23 +5,10 @@ "ref\01523980508.3310.9.camel@HansenPartnership.com\0" "ref\086252a65-265d-e081-b71f-42a0be6b1693@codeaurora.org\0" "ref\097fc18a7-b321-0039-0413-d461abc2097b@bell.net\0" - "From\0Sinan Kaya <okaya@codeaurora.org>\0" - "Subject\0Re: [PATCH v2 2/2] parisc: define stronger ordering for the default readX()\0" + "From\0okaya@codeaurora.org (Sinan Kaya)\0" + "Subject\0[PATCH v2 2/2] parisc: define stronger ordering for the default readX()\0" "Date\0Wed, 18 Apr 2018 09:39:30 -0400\0" - "To\0John David Anglin <dave.anglin@bell.net>" - James Bottomley <James.Bottomley@hansenpartnership.com> - linux-parisc@vger.kernel.org - arnd@arndb.de - timur@codeaurora.org - " sulrich@codeaurora.org\0" - "Cc\0linux-arm-msm@vger.kernel.org" - linux-arm-kernel@lists.infradead.org - Helge Deller <deller@gmx.de> - Philippe Ombredanne <pombredanne@nexb.com> - Kate Stewart <kstewart@linuxfoundation.org> - Thomas Gleixner <tglx@linutronix.de> - Greg Kroah-Hartman <gregkh@linuxfoundation.org> - " linux-kernel@vger.kernel.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On 4/17/2018 6:53 PM, John David Anglin wrote:\n" @@ -38,8 +25,8 @@ ">> writel() of PA-RISC needs to ensure that 3. cannot bypass 1. This is typically\n" ">> done by a write barrier embedded into the writel() on relaxed architectures.\n" "> The sequence point after the argument evaluation for writel prevents the compiler from reordering\n" - "> 1 and 2.\302\240 Accesses to I/O space are strongly ordered on PA-RISC, so 1 must occur before 2 (Page G-1\n" - "> of the PA-RISC 2.0 Architecture).\302\240 Thus, the current code is okay.\n" + "> 1 and 2.? Accesses to I/O space are strongly ordered on PA-RISC, so 1 must occur before 2 (Page G-1\n" + "> of the PA-RISC 2.0 Architecture).? Thus, the current code is okay.\n" "> \n" "\n" "Many thanks for the clarification.\n" @@ -53,4 +40,4 @@ "Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.\n" Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. -f815ff1fd42d99cdf0b02a808a3f89e539d9817c50e2eee604b1d72e805df468 +5bcd265279381ef82f0dae30e34b95327125c6ec7412c20acd8f9a3c56b28e66
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.