From: Sinan Kaya <okaya@codeaurora.org>
To: John David Anglin <dave.anglin@bell.net>,
James Bottomley <James.Bottomley@HansenPartnership.com>,
linux-parisc@vger.kernel.org, arnd@arndb.de,
timur@codeaurora.org, sulrich@codeaurora.org
Cc: linux-arm-msm@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Helge Deller <deller@gmx.de>,
Philippe Ombredanne <pombredanne@nexb.com>,
Kate Stewart <kstewart@linuxfoundation.org>,
Thomas Gleixner <tglx@linutronix.de>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 2/2] parisc: define stronger ordering for the default readX()
Date: Wed, 18 Apr 2018 09:39:30 -0400 [thread overview]
Message-ID: <a8c3391d-7109-47bf-e1c4-9217fc68bfd0@codeaurora.org> (raw)
In-Reply-To: <97fc18a7-b321-0039-0413-d461abc2097b@bell.net>
On 4/17/2018 6:53 PM, John David Anglin wrote:
> On 2018-04-17 2:28 PM, Sinan Kaya wrote:
>> The correct terminology here would be to use observability. Yes, it can be
>> cached in whatever part of the system for some amount of time as long as
>> PCI device sees it in the correct order.
>>
>> Let's do this exercise.
>> 1. OS writes to memory for some descriptor update
>> 2. OS writes to the device via writel to hit a doorbell
>> 3. Device comes and fetches the memory contents for the descriptor
>>
>> writel() of PA-RISC needs to ensure that 3. cannot bypass 1. This is typically
>> done by a write barrier embedded into the writel() on relaxed architectures.
> The sequence point after the argument evaluation for writel prevents the compiler from reordering
> 1 and 2. Accesses to I/O space are strongly ordered on PA-RISC, so 1 must occur before 2 (Page G-1
> of the PA-RISC 2.0 Architecture). Thus, the current code is okay.
>
Many thanks for the clarification.
> Dave
>
--
Sinan Kaya
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
WARNING: multiple messages have this Message-ID (diff)
From: okaya@codeaurora.org (Sinan Kaya)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 2/2] parisc: define stronger ordering for the default readX()
Date: Wed, 18 Apr 2018 09:39:30 -0400 [thread overview]
Message-ID: <a8c3391d-7109-47bf-e1c4-9217fc68bfd0@codeaurora.org> (raw)
In-Reply-To: <97fc18a7-b321-0039-0413-d461abc2097b@bell.net>
On 4/17/2018 6:53 PM, John David Anglin wrote:
> On 2018-04-17 2:28 PM, Sinan Kaya wrote:
>> The correct terminology here would be to use observability. Yes, it can be
>> cached in whatever part of the system for some amount of time as long as
>> PCI device sees it in the correct order.
>>
>> Let's do this exercise.
>> 1. OS writes to memory for some descriptor update
>> 2. OS writes to the device via writel to hit a doorbell
>> 3. Device comes and fetches the memory contents for the descriptor
>>
>> writel() of PA-RISC needs to ensure that 3. cannot bypass 1. This is typically
>> done by a write barrier embedded into the writel() on relaxed architectures.
> The sequence point after the argument evaluation for writel prevents the compiler from reordering
> 1 and 2.? Accesses to I/O space are strongly ordered on PA-RISC, so 1 must occur before 2 (Page G-1
> of the PA-RISC 2.0 Architecture).? Thus, the current code is okay.
>
Many thanks for the clarification.
> Dave
>
--
Sinan Kaya
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
next prev parent reply other threads:[~2018-04-18 13:39 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-04-17 4:08 [PATCH v2 1/2] parisc: define stronger ordering for the default writeX() Sinan Kaya
2018-04-17 4:08 ` Sinan Kaya
2018-04-17 4:08 ` [PATCH v2 2/2] parisc: define stronger ordering for the default readX() Sinan Kaya
2018-04-17 4:08 ` Sinan Kaya
2018-04-17 9:37 ` James Bottomley
2018-04-17 9:37 ` James Bottomley
2018-04-17 14:13 ` Sinan Kaya
2018-04-17 14:13 ` Sinan Kaya
2018-04-17 15:55 ` James Bottomley
2018-04-17 15:55 ` James Bottomley
2018-04-17 18:28 ` Sinan Kaya
2018-04-17 18:28 ` Sinan Kaya
2018-04-17 22:53 ` John David Anglin
2018-04-17 22:53 ` John David Anglin
2018-04-18 13:39 ` Sinan Kaya [this message]
2018-04-18 13:39 ` Sinan Kaya
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