* [PATCH RFC] target: riscv: Add Svrsw60b59b extension support
@ 2025-03-14 10:48 Alexandre Ghiti
2025-03-14 12:11 ` Alexandre Ghiti
2025-04-22 22:35 ` Deepak Gupta
0 siblings, 2 replies; 5+ messages in thread
From: Alexandre Ghiti @ 2025-03-14 10:48 UTC (permalink / raw)
To: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, qemu-riscv, qemu-devel
Cc: Alexandre Ghiti
The Svrsw60b59b extension allows to free the PTE reserved bits 60 and 59
for software to use.
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
---
I tested it by always setting the bits 60 and 59 in Linux which booted
fine.
target/riscv/cpu.c | 2 ++
target/riscv/cpu_bits.h | 3 ++-
target/riscv/cpu_cfg.h | 1 +
target/riscv/cpu_helper.c | 3 ++-
4 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3d4bd157d2..ee89cdef46 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -219,6 +219,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
+ ISA_EXT_DATA_ENTRY(svrsw60b59b, PRIV_VERSION_1_13_0, ext_svrsw60b59b),
ISA_EXT_DATA_ENTRY(svukte, PRIV_VERSION_1_13_0, ext_svukte),
ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc),
ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
@@ -1644,6 +1645,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false),
MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false),
MULTI_EXT_CFG_BOOL("svpbmt", ext_svpbmt, false),
+ MULTI_EXT_CFG_BOOL("svrsw60b59b", ext_svrsw60b59b, false),
MULTI_EXT_CFG_BOOL("svvptc", ext_svvptc, true),
MULTI_EXT_CFG_BOOL("zicntr", ext_zicntr, true),
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index f97c48a394..71f9e603c5 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -663,7 +663,8 @@ typedef enum {
#define PTE_SOFT 0x300 /* Reserved for Software */
#define PTE_PBMT 0x6000000000000000ULL /* Page-based memory types */
#define PTE_N 0x8000000000000000ULL /* NAPOT translation */
-#define PTE_RESERVED 0x1FC0000000000000ULL /* Reserved bits */
+#define PTE_RESERVED(svrsw60b59b) \
+ (svrsw60b59b ? 0x07C0000000000000ULL : 0x1FC0000000000000ULL) /* Reserved bits */
#define PTE_ATTR (PTE_N | PTE_PBMT) /* All attributes bits */
/* Page table PPN shift amount */
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index b410b1e603..f6e4b0068a 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -89,6 +89,7 @@ struct RISCVCPUConfig {
bool ext_svinval;
bool ext_svnapot;
bool ext_svpbmt;
+ bool ext_svrsw60b59b;
bool ext_svvptc;
bool ext_svukte;
bool ext_zdinx;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index e1dfc4ecbf..6546cea403 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1156,6 +1156,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
bool svade = riscv_cpu_cfg(env)->ext_svade;
bool svadu = riscv_cpu_cfg(env)->ext_svadu;
bool adue = svadu ? env->menvcfg & MENVCFG_ADUE : !svade;
+ bool svrsw60b59b = riscv_cpu_cfg(env)->ext_svrsw60b59b;
if (first_stage && two_stage && env->virt_enabled) {
pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
@@ -1225,7 +1226,7 @@ restart:
if (riscv_cpu_sxl(env) == MXL_RV32) {
ppn = pte >> PTE_PPN_SHIFT;
} else {
- if (pte & PTE_RESERVED) {
+ if (pte & PTE_RESERVED(svrsw60b59b)) {
return TRANSLATE_FAIL;
}
--
2.39.2
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH RFC] target: riscv: Add Svrsw60b59b extension support
2025-03-14 10:48 [PATCH RFC] target: riscv: Add Svrsw60b59b extension support Alexandre Ghiti
@ 2025-03-14 12:11 ` Alexandre Ghiti
2025-03-14 12:38 ` Daniel Henrique Barboza
2025-04-22 22:35 ` Deepak Gupta
1 sibling, 1 reply; 5+ messages in thread
From: Alexandre Ghiti @ 2025-03-14 12:11 UTC (permalink / raw)
To: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, qemu-riscv, qemu-devel
On Fri, Mar 14, 2025 at 11:48 AM Alexandre Ghiti <alexghiti@rivosinc.com> wrote:
>
> The Svrsw60b59b extension allows to free the PTE reserved bits 60 and 59
> for software to use.
I missed that the extension had been renamed to Svrsw60*t*59b, I'll
fix that in v2 later after I collect some feedback.
Thanks,
Alex
>
> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
> ---
>
> I tested it by always setting the bits 60 and 59 in Linux which booted
> fine.
>
> target/riscv/cpu.c | 2 ++
> target/riscv/cpu_bits.h | 3 ++-
> target/riscv/cpu_cfg.h | 1 +
> target/riscv/cpu_helper.c | 3 ++-
> 4 files changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 3d4bd157d2..ee89cdef46 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -219,6 +219,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
> ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
> ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
> ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
> + ISA_EXT_DATA_ENTRY(svrsw60b59b, PRIV_VERSION_1_13_0, ext_svrsw60b59b),
> ISA_EXT_DATA_ENTRY(svukte, PRIV_VERSION_1_13_0, ext_svukte),
> ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc),
> ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
> @@ -1644,6 +1645,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
> MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false),
> MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false),
> MULTI_EXT_CFG_BOOL("svpbmt", ext_svpbmt, false),
> + MULTI_EXT_CFG_BOOL("svrsw60b59b", ext_svrsw60b59b, false),
> MULTI_EXT_CFG_BOOL("svvptc", ext_svvptc, true),
>
> MULTI_EXT_CFG_BOOL("zicntr", ext_zicntr, true),
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index f97c48a394..71f9e603c5 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -663,7 +663,8 @@ typedef enum {
> #define PTE_SOFT 0x300 /* Reserved for Software */
> #define PTE_PBMT 0x6000000000000000ULL /* Page-based memory types */
> #define PTE_N 0x8000000000000000ULL /* NAPOT translation */
> -#define PTE_RESERVED 0x1FC0000000000000ULL /* Reserved bits */
> +#define PTE_RESERVED(svrsw60b59b) \
> + (svrsw60b59b ? 0x07C0000000000000ULL : 0x1FC0000000000000ULL) /* Reserved bits */
> #define PTE_ATTR (PTE_N | PTE_PBMT) /* All attributes bits */
>
> /* Page table PPN shift amount */
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index b410b1e603..f6e4b0068a 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -89,6 +89,7 @@ struct RISCVCPUConfig {
> bool ext_svinval;
> bool ext_svnapot;
> bool ext_svpbmt;
> + bool ext_svrsw60b59b;
> bool ext_svvptc;
> bool ext_svukte;
> bool ext_zdinx;
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index e1dfc4ecbf..6546cea403 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -1156,6 +1156,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
> bool svade = riscv_cpu_cfg(env)->ext_svade;
> bool svadu = riscv_cpu_cfg(env)->ext_svadu;
> bool adue = svadu ? env->menvcfg & MENVCFG_ADUE : !svade;
> + bool svrsw60b59b = riscv_cpu_cfg(env)->ext_svrsw60b59b;
>
> if (first_stage && two_stage && env->virt_enabled) {
> pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
> @@ -1225,7 +1226,7 @@ restart:
> if (riscv_cpu_sxl(env) == MXL_RV32) {
> ppn = pte >> PTE_PPN_SHIFT;
> } else {
> - if (pte & PTE_RESERVED) {
> + if (pte & PTE_RESERVED(svrsw60b59b)) {
> return TRANSLATE_FAIL;
> }
>
> --
> 2.39.2
>
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH RFC] target: riscv: Add Svrsw60b59b extension support
2025-03-14 12:11 ` Alexandre Ghiti
@ 2025-03-14 12:38 ` Daniel Henrique Barboza
2025-03-14 13:31 ` Alexandre Ghiti
0 siblings, 1 reply; 5+ messages in thread
From: Daniel Henrique Barboza @ 2025-03-14 12:38 UTC (permalink / raw)
To: Alexandre Ghiti, Palmer Dabbelt, Alistair Francis, Bin Meng,
Weiwei Li, Liu Zhiwei, qemu-riscv, qemu-devel
On 3/14/25 9:11 AM, Alexandre Ghiti wrote:
> On Fri, Mar 14, 2025 at 11:48 AM Alexandre Ghiti <alexghiti@rivosinc.com> wrote:
>>
>> The Svrsw60b59b extension allows to free the PTE reserved bits 60 and 59
>> for software to use.
>
> I missed that the extension had been renamed to Svrsw60*t*59b, I'll
> fix that in v2 later after I collect some feedback.
Just to be clear: the extension is going to be named Svrsw60t59b, not
"Svrsw60*t*59b". Correct?
Aside from that code LGTM. Thanks,
Daniel
>
> Thanks,
>
> Alex
>
>>
>> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
>> ---
>>
>> I tested it by always setting the bits 60 and 59 in Linux which booted
>> fine.
>>
>> target/riscv/cpu.c | 2 ++
>> target/riscv/cpu_bits.h | 3 ++-
>> target/riscv/cpu_cfg.h | 1 +
>> target/riscv/cpu_helper.c | 3 ++-
>> 4 files changed, 7 insertions(+), 2 deletions(-)
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index 3d4bd157d2..ee89cdef46 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -219,6 +219,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
>> ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
>> ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
>> ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
>> + ISA_EXT_DATA_ENTRY(svrsw60b59b, PRIV_VERSION_1_13_0, ext_svrsw60b59b),
>> ISA_EXT_DATA_ENTRY(svukte, PRIV_VERSION_1_13_0, ext_svukte),
>> ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc),
>> ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
>> @@ -1644,6 +1645,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
>> MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false),
>> MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false),
>> MULTI_EXT_CFG_BOOL("svpbmt", ext_svpbmt, false),
>> + MULTI_EXT_CFG_BOOL("svrsw60b59b", ext_svrsw60b59b, false),
>> MULTI_EXT_CFG_BOOL("svvptc", ext_svvptc, true),
>>
>> MULTI_EXT_CFG_BOOL("zicntr", ext_zicntr, true),
>> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
>> index f97c48a394..71f9e603c5 100644
>> --- a/target/riscv/cpu_bits.h
>> +++ b/target/riscv/cpu_bits.h
>> @@ -663,7 +663,8 @@ typedef enum {
>> #define PTE_SOFT 0x300 /* Reserved for Software */
>> #define PTE_PBMT 0x6000000000000000ULL /* Page-based memory types */
>> #define PTE_N 0x8000000000000000ULL /* NAPOT translation */
>> -#define PTE_RESERVED 0x1FC0000000000000ULL /* Reserved bits */
>> +#define PTE_RESERVED(svrsw60b59b) \
>> + (svrsw60b59b ? 0x07C0000000000000ULL : 0x1FC0000000000000ULL) /* Reserved bits */
>> #define PTE_ATTR (PTE_N | PTE_PBMT) /* All attributes bits */
>>
>> /* Page table PPN shift amount */
>> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
>> index b410b1e603..f6e4b0068a 100644
>> --- a/target/riscv/cpu_cfg.h
>> +++ b/target/riscv/cpu_cfg.h
>> @@ -89,6 +89,7 @@ struct RISCVCPUConfig {
>> bool ext_svinval;
>> bool ext_svnapot;
>> bool ext_svpbmt;
>> + bool ext_svrsw60b59b;
>> bool ext_svvptc;
>> bool ext_svukte;
>> bool ext_zdinx;
>> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
>> index e1dfc4ecbf..6546cea403 100644
>> --- a/target/riscv/cpu_helper.c
>> +++ b/target/riscv/cpu_helper.c
>> @@ -1156,6 +1156,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
>> bool svade = riscv_cpu_cfg(env)->ext_svade;
>> bool svadu = riscv_cpu_cfg(env)->ext_svadu;
>> bool adue = svadu ? env->menvcfg & MENVCFG_ADUE : !svade;
>> + bool svrsw60b59b = riscv_cpu_cfg(env)->ext_svrsw60b59b;
>>
>> if (first_stage && two_stage && env->virt_enabled) {
>> pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
>> @@ -1225,7 +1226,7 @@ restart:
>> if (riscv_cpu_sxl(env) == MXL_RV32) {
>> ppn = pte >> PTE_PPN_SHIFT;
>> } else {
>> - if (pte & PTE_RESERVED) {
>> + if (pte & PTE_RESERVED(svrsw60b59b)) {
>> return TRANSLATE_FAIL;
>> }
>>
>> --
>> 2.39.2
>>
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH RFC] target: riscv: Add Svrsw60b59b extension support
2025-03-14 12:38 ` Daniel Henrique Barboza
@ 2025-03-14 13:31 ` Alexandre Ghiti
0 siblings, 0 replies; 5+ messages in thread
From: Alexandre Ghiti @ 2025-03-14 13:31 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Liu Zhiwei,
qemu-riscv, qemu-devel
On Fri, Mar 14, 2025 at 1:38 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
>
>
> On 3/14/25 9:11 AM, Alexandre Ghiti wrote:
> > On Fri, Mar 14, 2025 at 11:48 AM Alexandre Ghiti <alexghiti@rivosinc.com> wrote:
> >>
> >> The Svrsw60b59b extension allows to free the PTE reserved bits 60 and 59
> >> for software to use.
> >
> > I missed that the extension had been renamed to Svrsw60*t*59b, I'll
> > fix that in v2 later after I collect some feedback.
>
> Just to be clear: the extension is going to be named Svrsw60t59b, not
> "Svrsw60*t*59b". Correct?
Yes, I added the '*' to emphasize the subtle change :)
>
>
> Aside from that code LGTM. Thanks,
Thanks!
Alex
>
> Daniel
>
>
> >
> > Thanks,
> >
> > Alex
> >
> >>
> >> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
> >> ---
> >>
> >> I tested it by always setting the bits 60 and 59 in Linux which booted
> >> fine.
> >>
> >> target/riscv/cpu.c | 2 ++
> >> target/riscv/cpu_bits.h | 3 ++-
> >> target/riscv/cpu_cfg.h | 1 +
> >> target/riscv/cpu_helper.c | 3 ++-
> >> 4 files changed, 7 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> >> index 3d4bd157d2..ee89cdef46 100644
> >> --- a/target/riscv/cpu.c
> >> +++ b/target/riscv/cpu.c
> >> @@ -219,6 +219,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
> >> ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
> >> ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
> >> ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
> >> + ISA_EXT_DATA_ENTRY(svrsw60b59b, PRIV_VERSION_1_13_0, ext_svrsw60b59b),
> >> ISA_EXT_DATA_ENTRY(svukte, PRIV_VERSION_1_13_0, ext_svukte),
> >> ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc),
> >> ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
> >> @@ -1644,6 +1645,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
> >> MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false),
> >> MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false),
> >> MULTI_EXT_CFG_BOOL("svpbmt", ext_svpbmt, false),
> >> + MULTI_EXT_CFG_BOOL("svrsw60b59b", ext_svrsw60b59b, false),
> >> MULTI_EXT_CFG_BOOL("svvptc", ext_svvptc, true),
> >>
> >> MULTI_EXT_CFG_BOOL("zicntr", ext_zicntr, true),
> >> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> >> index f97c48a394..71f9e603c5 100644
> >> --- a/target/riscv/cpu_bits.h
> >> +++ b/target/riscv/cpu_bits.h
> >> @@ -663,7 +663,8 @@ typedef enum {
> >> #define PTE_SOFT 0x300 /* Reserved for Software */
> >> #define PTE_PBMT 0x6000000000000000ULL /* Page-based memory types */
> >> #define PTE_N 0x8000000000000000ULL /* NAPOT translation */
> >> -#define PTE_RESERVED 0x1FC0000000000000ULL /* Reserved bits */
> >> +#define PTE_RESERVED(svrsw60b59b) \
> >> + (svrsw60b59b ? 0x07C0000000000000ULL : 0x1FC0000000000000ULL) /* Reserved bits */
> >> #define PTE_ATTR (PTE_N | PTE_PBMT) /* All attributes bits */
> >>
> >> /* Page table PPN shift amount */
> >> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> >> index b410b1e603..f6e4b0068a 100644
> >> --- a/target/riscv/cpu_cfg.h
> >> +++ b/target/riscv/cpu_cfg.h
> >> @@ -89,6 +89,7 @@ struct RISCVCPUConfig {
> >> bool ext_svinval;
> >> bool ext_svnapot;
> >> bool ext_svpbmt;
> >> + bool ext_svrsw60b59b;
> >> bool ext_svvptc;
> >> bool ext_svukte;
> >> bool ext_zdinx;
> >> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> >> index e1dfc4ecbf..6546cea403 100644
> >> --- a/target/riscv/cpu_helper.c
> >> +++ b/target/riscv/cpu_helper.c
> >> @@ -1156,6 +1156,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
> >> bool svade = riscv_cpu_cfg(env)->ext_svade;
> >> bool svadu = riscv_cpu_cfg(env)->ext_svadu;
> >> bool adue = svadu ? env->menvcfg & MENVCFG_ADUE : !svade;
> >> + bool svrsw60b59b = riscv_cpu_cfg(env)->ext_svrsw60b59b;
> >>
> >> if (first_stage && two_stage && env->virt_enabled) {
> >> pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
> >> @@ -1225,7 +1226,7 @@ restart:
> >> if (riscv_cpu_sxl(env) == MXL_RV32) {
> >> ppn = pte >> PTE_PPN_SHIFT;
> >> } else {
> >> - if (pte & PTE_RESERVED) {
> >> + if (pte & PTE_RESERVED(svrsw60b59b)) {
> >> return TRANSLATE_FAIL;
> >> }
> >>
> >> --
> >> 2.39.2
> >>
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH RFC] target: riscv: Add Svrsw60b59b extension support
2025-03-14 10:48 [PATCH RFC] target: riscv: Add Svrsw60b59b extension support Alexandre Ghiti
2025-03-14 12:11 ` Alexandre Ghiti
@ 2025-04-22 22:35 ` Deepak Gupta
1 sibling, 0 replies; 5+ messages in thread
From: Deepak Gupta @ 2025-04-22 22:35 UTC (permalink / raw)
To: Alexandre Ghiti
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, qemu-riscv, qemu-devel
On Fri, Mar 14, 2025 at 11:48:33AM +0100, Alexandre Ghiti wrote:
>The Svrsw60b59b extension allows to free the PTE reserved bits 60 and 59
>for software to use.
Apart from what you already caught.
Extension is dependnet on Sv39. So it should be validated somewhere.
Perhaps in `riscv_cpu_validate_set_extensions` (target/riscv/tcg/tcg-cpu.c).
>
>Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
>---
>
>I tested it by always setting the bits 60 and 59 in Linux which booted
>fine.
>
> target/riscv/cpu.c | 2 ++
> target/riscv/cpu_bits.h | 3 ++-
> target/riscv/cpu_cfg.h | 1 +
> target/riscv/cpu_helper.c | 3 ++-
> 4 files changed, 7 insertions(+), 2 deletions(-)
>
>diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>index 3d4bd157d2..ee89cdef46 100644
>--- a/target/riscv/cpu.c
>+++ b/target/riscv/cpu.c
>@@ -219,6 +219,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
> ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
> ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
> ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
>+ ISA_EXT_DATA_ENTRY(svrsw60b59b, PRIV_VERSION_1_13_0, ext_svrsw60b59b),
> ISA_EXT_DATA_ENTRY(svukte, PRIV_VERSION_1_13_0, ext_svukte),
> ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc),
> ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
>@@ -1644,6 +1645,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
> MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false),
> MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false),
> MULTI_EXT_CFG_BOOL("svpbmt", ext_svpbmt, false),
>+ MULTI_EXT_CFG_BOOL("svrsw60b59b", ext_svrsw60b59b, false),
> MULTI_EXT_CFG_BOOL("svvptc", ext_svvptc, true),
>
> MULTI_EXT_CFG_BOOL("zicntr", ext_zicntr, true),
>diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
>index f97c48a394..71f9e603c5 100644
>--- a/target/riscv/cpu_bits.h
>+++ b/target/riscv/cpu_bits.h
>@@ -663,7 +663,8 @@ typedef enum {
> #define PTE_SOFT 0x300 /* Reserved for Software */
> #define PTE_PBMT 0x6000000000000000ULL /* Page-based memory types */
> #define PTE_N 0x8000000000000000ULL /* NAPOT translation */
>-#define PTE_RESERVED 0x1FC0000000000000ULL /* Reserved bits */
>+#define PTE_RESERVED(svrsw60b59b) \
>+ (svrsw60b59b ? 0x07C0000000000000ULL : 0x1FC0000000000000ULL) /* Reserved bits */
> #define PTE_ATTR (PTE_N | PTE_PBMT) /* All attributes bits */
>
> /* Page table PPN shift amount */
>diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
>index b410b1e603..f6e4b0068a 100644
>--- a/target/riscv/cpu_cfg.h
>+++ b/target/riscv/cpu_cfg.h
>@@ -89,6 +89,7 @@ struct RISCVCPUConfig {
> bool ext_svinval;
> bool ext_svnapot;
> bool ext_svpbmt;
>+ bool ext_svrsw60b59b;
> bool ext_svvptc;
> bool ext_svukte;
> bool ext_zdinx;
>diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
>index e1dfc4ecbf..6546cea403 100644
>--- a/target/riscv/cpu_helper.c
>+++ b/target/riscv/cpu_helper.c
>@@ -1156,6 +1156,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
> bool svade = riscv_cpu_cfg(env)->ext_svade;
> bool svadu = riscv_cpu_cfg(env)->ext_svadu;
> bool adue = svadu ? env->menvcfg & MENVCFG_ADUE : !svade;
>+ bool svrsw60b59b = riscv_cpu_cfg(env)->ext_svrsw60b59b;
>
> if (first_stage && two_stage && env->virt_enabled) {
> pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
>@@ -1225,7 +1226,7 @@ restart:
> if (riscv_cpu_sxl(env) == MXL_RV32) {
> ppn = pte >> PTE_PPN_SHIFT;
> } else {
>- if (pte & PTE_RESERVED) {
>+ if (pte & PTE_RESERVED(svrsw60b59b)) {
> return TRANSLATE_FAIL;
> }
>
>--
>2.39.2
>
>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2025-04-22 22:35 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-03-14 10:48 [PATCH RFC] target: riscv: Add Svrsw60b59b extension support Alexandre Ghiti
2025-03-14 12:11 ` Alexandre Ghiti
2025-03-14 12:38 ` Daniel Henrique Barboza
2025-03-14 13:31 ` Alexandre Ghiti
2025-04-22 22:35 ` Deepak Gupta
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