* [PATCH] drm/amdgpu: remove mdelay in psp v12 @ 2025-04-22 4:16 Huang Rui 2025-04-29 13:45 ` Huang Rui 0 siblings, 1 reply; 3+ messages in thread From: Huang Rui @ 2025-04-22 4:16 UTC (permalink / raw) To: Alex Deucher, Christian König, amd-gfx Cc: Trigger Huang, Zhu Lingshan, Huang Rui Since secure firmware is more stable than bring up phase, I believe we don't need such mdelays any more before wait PSP response on PSP v12. Signed-off-by: Huang Rui <ray.huang@amd.com> --- drivers/gpu/drm/amd/amdgpu/psp_v12_0.c | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c index fcd708eae75c..6331941440d9 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c @@ -99,9 +99,6 @@ static int psp_v12_0_bootloader_load_sysdrv(struct psp_context *psp) WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, psp_gfxdrv_command_reg); - /* there might be handshake issue with hardware which needs delay */ - mdelay(20); - ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 0x80000000, 0x80000000, false); @@ -138,8 +135,6 @@ static int psp_v12_0_bootloader_load_sos(struct psp_context *psp) WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, psp_gfxdrv_command_reg); - /* there might be handshake issue with hardware which needs delay */ - mdelay(20); ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 0, true); @@ -161,7 +156,6 @@ static void psp_v12_0_reroute_ih(struct psp_context *psp) WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); - mdelay(20); psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 0x80000000, 0x8000FFFF, false); @@ -173,7 +167,6 @@ static void psp_v12_0_reroute_ih(struct psp_context *psp) WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); - mdelay(20); psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 0x80000000, 0x8000FFFF, false); } @@ -200,9 +193,6 @@ static int psp_v12_0_ring_create(struct psp_context *psp, WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_INIT_GPCOM_RING); - /* there might be handshake issue with hardware which needs delay */ - mdelay(20); - /* Wait for response flag (bit 31) in C2PMSG_101 */ ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 0x80000000, 0x8000FFFF, false); @@ -222,9 +212,6 @@ static int psp_v12_0_ring_create(struct psp_context *psp, psp_ring_reg = psp_ring_reg << 16; WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); - /* there might be handshake issue with hardware which needs delay */ - mdelay(20); - /* Wait for response flag (bit 31) in C2PMSG_64 */ ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 0x80000000, 0x8000FFFF, false); @@ -247,9 +234,6 @@ static int psp_v12_0_ring_stop(struct psp_context *psp, WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_DESTROY_RINGS); - /* there might be handshake issue with hardware which needs delay */ - mdelay(20); - /* Wait for response flag (bit 31) */ if (amdgpu_sriov_vf(adev)) ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), -- 2.25.1 ^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] drm/amdgpu: remove mdelay in psp v12 2025-04-22 4:16 [PATCH] drm/amdgpu: remove mdelay in psp v12 Huang Rui @ 2025-04-29 13:45 ` Huang Rui 2025-05-07 6:29 ` Huang, Trigger 0 siblings, 1 reply; 3+ messages in thread From: Huang Rui @ 2025-04-29 13:45 UTC (permalink / raw) To: Alex Deucher, Christian König, amd-gfx; +Cc: Trigger Huang, Zhu Lingshan Soft ping~ On Tue, Apr 22, 2025 at 12:16:29PM +0800, Huang Rui wrote: > Since secure firmware is more stable than bring up phase, I believe we > don't need such mdelays any more before wait PSP response on PSP v12. > > Signed-off-by: Huang Rui <ray.huang@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/psp_v12_0.c | 16 ---------------- > 1 file changed, 16 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c > index fcd708eae75c..6331941440d9 100644 > --- a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c > @@ -99,9 +99,6 @@ static int psp_v12_0_bootloader_load_sysdrv(struct psp_context *psp) > WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, > psp_gfxdrv_command_reg); > > - /* there might be handshake issue with hardware which needs delay */ > - mdelay(20); > - > ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), > 0x80000000, 0x80000000, false); > > @@ -138,8 +135,6 @@ static int psp_v12_0_bootloader_load_sos(struct psp_context *psp) > WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, > psp_gfxdrv_command_reg); > > - /* there might be handshake issue with hardware which needs delay */ > - mdelay(20); > ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), > RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), > 0, true); > @@ -161,7 +156,6 @@ static void psp_v12_0_reroute_ih(struct psp_context *psp) > WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); > WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); > > - mdelay(20); > psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), > 0x80000000, 0x8000FFFF, false); > > @@ -173,7 +167,6 @@ static void psp_v12_0_reroute_ih(struct psp_context *psp) > WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); > WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); > > - mdelay(20); > psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), > 0x80000000, 0x8000FFFF, false); > } > @@ -200,9 +193,6 @@ static int psp_v12_0_ring_create(struct psp_context *psp, > WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, > GFX_CTRL_CMD_ID_INIT_GPCOM_RING); > > - /* there might be handshake issue with hardware which needs delay */ > - mdelay(20); > - > /* Wait for response flag (bit 31) in C2PMSG_101 */ > ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), > 0x80000000, 0x8000FFFF, false); > @@ -222,9 +212,6 @@ static int psp_v12_0_ring_create(struct psp_context *psp, > psp_ring_reg = psp_ring_reg << 16; > WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); > > - /* there might be handshake issue with hardware which needs delay */ > - mdelay(20); > - > /* Wait for response flag (bit 31) in C2PMSG_64 */ > ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), > 0x80000000, 0x8000FFFF, false); > @@ -247,9 +234,6 @@ static int psp_v12_0_ring_stop(struct psp_context *psp, > WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, > GFX_CTRL_CMD_ID_DESTROY_RINGS); > > - /* there might be handshake issue with hardware which needs delay */ > - mdelay(20); > - > /* Wait for response flag (bit 31) */ > if (amdgpu_sriov_vf(adev)) > ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), > -- > 2.25.1 > ^ permalink raw reply [flat|nested] 3+ messages in thread
* RE: [PATCH] drm/amdgpu: remove mdelay in psp v12 2025-04-29 13:45 ` Huang Rui @ 2025-05-07 6:29 ` Huang, Trigger 0 siblings, 0 replies; 3+ messages in thread From: Huang, Trigger @ 2025-05-07 6:29 UTC (permalink / raw) To: Huang, Ray, Deucher, Alexander, Koenig, Christian, amd-gfx@lists.freedesktop.org Cc: Zhu, Lingshan [AMD Official Use Only - AMD Internal Distribution Only] > -----Original Message----- > From: Huang, Ray <Ray.Huang@amd.com> > Sent: Tuesday, April 29, 2025 9:46 PM > To: Deucher, Alexander <Alexander.Deucher@amd.com>; Koenig, Christian > <Christian.Koenig@amd.com>; amd-gfx@lists.freedesktop.org > Cc: Huang, Trigger <Trigger.Huang@amd.com>; Zhu, Lingshan > <Lingshan.Zhu@amd.com> > Subject: Re: [PATCH] drm/amdgpu: remove mdelay in psp v12 > > Soft ping~ > > On Tue, Apr 22, 2025 at 12:16:29PM +0800, Huang Rui wrote: > > Since secure firmware is more stable than bring up phase, I believe we > > don't need such mdelays any more before wait PSP response on PSP v12. > > > > Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Trigger Huang <Trigger.Huang@amd.com> > > --- > > drivers/gpu/drm/amd/amdgpu/psp_v12_0.c | 16 ---------------- > > 1 file changed, 16 deletions(-) > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c > > b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c > > index fcd708eae75c..6331941440d9 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c > > @@ -99,9 +99,6 @@ static int psp_v12_0_bootloader_load_sysdrv(struct > psp_context *psp) > > WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, > > psp_gfxdrv_command_reg); > > > > - /* there might be handshake issue with hardware which needs delay */ > > - mdelay(20); > > - > > ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, > mmMP0_SMN_C2PMSG_35), > > 0x80000000, 0x80000000, false); > > > > @@ -138,8 +135,6 @@ static int psp_v12_0_bootloader_load_sos(struct > psp_context *psp) > > WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, > > psp_gfxdrv_command_reg); > > > > - /* there might be handshake issue with hardware which needs delay */ > > - mdelay(20); > > ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, > mmMP0_SMN_C2PMSG_81), > > RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), > > 0, true); > > @@ -161,7 +156,6 @@ static void psp_v12_0_reroute_ih(struct psp_context > *psp) > > WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); > > WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, > > GFX_CTRL_CMD_ID_GBR_IH_SET); > > > > - mdelay(20); > > psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, > mmMP0_SMN_C2PMSG_64), > > 0x80000000, 0x8000FFFF, false); > > > > @@ -173,7 +167,6 @@ static void psp_v12_0_reroute_ih(struct psp_context > *psp) > > WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); > > WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, > > GFX_CTRL_CMD_ID_GBR_IH_SET); > > > > - mdelay(20); > > psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, > mmMP0_SMN_C2PMSG_64), > > 0x80000000, 0x8000FFFF, false); } @@ -200,9 +193,6 @@ > static > > int psp_v12_0_ring_create(struct psp_context *psp, > > WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, > > > GFX_CTRL_CMD_ID_INIT_GPCOM_RING); > > > > - /* there might be handshake issue with hardware which needs delay > */ > > - mdelay(20); > > - > > /* Wait for response flag (bit 31) in C2PMSG_101 */ > > ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, > mmMP0_SMN_C2PMSG_101), > > 0x80000000, 0x8000FFFF, false); @@ -222,9 > +212,6 @@ static int > > psp_v12_0_ring_create(struct psp_context *psp, > > psp_ring_reg = psp_ring_reg << 16; > > WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, > psp_ring_reg); > > > > - /* there might be handshake issue with hardware which needs delay > */ > > - mdelay(20); > > - > > /* Wait for response flag (bit 31) in C2PMSG_64 */ > > ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, > mmMP0_SMN_C2PMSG_64), > > 0x80000000, 0x8000FFFF, false); @@ -247,9 > +234,6 @@ static int > > psp_v12_0_ring_stop(struct psp_context *psp, > > WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, > > GFX_CTRL_CMD_ID_DESTROY_RINGS); > > > > - /* there might be handshake issue with hardware which needs delay */ > > - mdelay(20); > > - > > /* Wait for response flag (bit 31) */ > > if (amdgpu_sriov_vf(adev)) > > ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, > > mmMP0_SMN_C2PMSG_101), > > -- > > 2.25.1 > > ^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2025-05-07 6:29 UTC | newest] Thread overview: 3+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-04-22 4:16 [PATCH] drm/amdgpu: remove mdelay in psp v12 Huang Rui 2025-04-29 13:45 ` Huang Rui 2025-05-07 6:29 ` Huang, Trigger
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