* [PATCH 1/2] drm/amdgpu: remove re-route ih in psp v12
@ 2025-04-29 10:29 Huang Rui
2025-04-29 10:29 ` [PATCH 2/2] drm/amdgpu: cleanup sriov function for " Huang Rui
2025-04-29 13:50 ` [PATCH 1/2] drm/amdgpu: remove re-route ih in " Christian König
0 siblings, 2 replies; 6+ messages in thread
From: Huang Rui @ 2025-04-29 10:29 UTC (permalink / raw)
To: Alex Deucher, Christian König, amd-gfx
Cc: Trigger Huang, Zhu Lingshan, Huang Rui
APU doesn't have second IH ring, so re-routing action here is a no-op.
It will take a lot of time to wait timeout from PSP during the
initialization. So remove the function in psp v12.
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/psp_v12_0.c | 34 --------------------------
1 file changed, 34 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
index 6331941440d9..ed24f61e1ab8 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
@@ -34,9 +34,6 @@
#include "sdma0/sdma0_4_0_offset.h"
#include "nbio/nbio_7_4_offset.h"
-#include "oss/osssys_4_0_offset.h"
-#include "oss/osssys_4_0_sh_mask.h"
-
MODULE_FIRMWARE("amdgpu/renoir_asd.bin");
MODULE_FIRMWARE("amdgpu/renoir_ta.bin");
MODULE_FIRMWARE("amdgpu/green_sardine_asd.bin");
@@ -142,35 +139,6 @@ static int psp_v12_0_bootloader_load_sos(struct psp_context *psp)
return ret;
}
-static void psp_v12_0_reroute_ih(struct psp_context *psp)
-{
- struct amdgpu_device *adev = psp->adev;
- uint32_t tmp;
-
- /* Change IH ring for VMC */
- tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
- tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
- tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
-
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
-
- psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
- 0x80000000, 0x8000FFFF, false);
-
- /* Change IH ring for UMC */
- tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
- tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
-
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
-
- psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
- 0x80000000, 0x8000FFFF, false);
-}
-
static int psp_v12_0_ring_create(struct psp_context *psp,
enum psp_ring_type ring_type)
{
@@ -179,8 +147,6 @@ static int psp_v12_0_ring_create(struct psp_context *psp,
struct psp_ring *ring = &psp->km_ring;
struct amdgpu_device *adev = psp->adev;
- psp_v12_0_reroute_ih(psp);
-
if (amdgpu_sriov_vf(psp->adev)) {
/* Write low address of the ring to C2PMSG_102 */
psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] drm/amdgpu: cleanup sriov function for psp v12
2025-04-29 10:29 [PATCH 1/2] drm/amdgpu: remove re-route ih in psp v12 Huang Rui
@ 2025-04-29 10:29 ` Huang Rui
2025-04-29 13:23 ` Alex Deucher
2025-04-29 13:50 ` [PATCH 1/2] drm/amdgpu: remove re-route ih in " Christian König
1 sibling, 1 reply; 6+ messages in thread
From: Huang Rui @ 2025-04-29 10:29 UTC (permalink / raw)
To: Alex Deucher, Christian König, amd-gfx
Cc: Trigger Huang, Zhu Lingshan, Huang Rui
PSP v12 won't have SRIOV function.
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/psp_v12_0.c | 52 +++++++++-----------------
1 file changed, 17 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
index ed24f61e1ab8..80153f837470 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
@@ -147,41 +147,23 @@ static int psp_v12_0_ring_create(struct psp_context *psp,
struct psp_ring *ring = &psp->km_ring;
struct amdgpu_device *adev = psp->adev;
- if (amdgpu_sriov_vf(psp->adev)) {
- /* Write low address of the ring to C2PMSG_102 */
- psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
- /* Write high address of the ring to C2PMSG_103 */
- psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
-
- /* Write the ring initialization command to C2PMSG_101 */
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
- GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
-
- /* Wait for response flag (bit 31) in C2PMSG_101 */
- ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
- 0x80000000, 0x8000FFFF, false);
-
- } else {
- /* Write low address of the ring to C2PMSG_69 */
- psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
- /* Write high address of the ring to C2PMSG_70 */
- psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
- /* Write size of ring to C2PMSG_71 */
- psp_ring_reg = ring->ring_size;
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
- /* Write the ring initialization command to C2PMSG_64 */
- psp_ring_reg = ring_type;
- psp_ring_reg = psp_ring_reg << 16;
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
-
- /* Wait for response flag (bit 31) in C2PMSG_64 */
- ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
- 0x80000000, 0x8000FFFF, false);
- }
+ /* Write low address of the ring to C2PMSG_69 */
+ psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
+ /* Write high address of the ring to C2PMSG_70 */
+ psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
+ /* Write size of ring to C2PMSG_71 */
+ psp_ring_reg = ring->ring_size;
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
+ /* Write the ring initialization command to C2PMSG_64 */
+ psp_ring_reg = ring_type;
+ psp_ring_reg = psp_ring_reg << 16;
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
+
+ /* Wait for response flag (bit 31) in C2PMSG_64 */
+ ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
+ 0x80000000, 0x8000FFFF, false);
return ret;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] drm/amdgpu: cleanup sriov function for psp v12
2025-04-29 10:29 ` [PATCH 2/2] drm/amdgpu: cleanup sriov function for " Huang Rui
@ 2025-04-29 13:23 ` Alex Deucher
0 siblings, 0 replies; 6+ messages in thread
From: Alex Deucher @ 2025-04-29 13:23 UTC (permalink / raw)
To: Huang Rui
Cc: Alex Deucher, Christian König, amd-gfx, Trigger Huang,
Zhu Lingshan
Series is:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
On Tue, Apr 29, 2025 at 6:30 AM Huang Rui <ray.huang@amd.com> wrote:
>
> PSP v12 won't have SRIOV function.
>
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/psp_v12_0.c | 52 +++++++++-----------------
> 1 file changed, 17 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
> index ed24f61e1ab8..80153f837470 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
> @@ -147,41 +147,23 @@ static int psp_v12_0_ring_create(struct psp_context *psp,
> struct psp_ring *ring = &psp->km_ring;
> struct amdgpu_device *adev = psp->adev;
>
> - if (amdgpu_sriov_vf(psp->adev)) {
> - /* Write low address of the ring to C2PMSG_102 */
> - psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
> - WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
> - /* Write high address of the ring to C2PMSG_103 */
> - psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
> - WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
> -
> - /* Write the ring initialization command to C2PMSG_101 */
> - WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
> - GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
> -
> - /* Wait for response flag (bit 31) in C2PMSG_101 */
> - ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
> - 0x80000000, 0x8000FFFF, false);
> -
> - } else {
> - /* Write low address of the ring to C2PMSG_69 */
> - psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
> - WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
> - /* Write high address of the ring to C2PMSG_70 */
> - psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
> - WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
> - /* Write size of ring to C2PMSG_71 */
> - psp_ring_reg = ring->ring_size;
> - WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
> - /* Write the ring initialization command to C2PMSG_64 */
> - psp_ring_reg = ring_type;
> - psp_ring_reg = psp_ring_reg << 16;
> - WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
> -
> - /* Wait for response flag (bit 31) in C2PMSG_64 */
> - ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
> - 0x80000000, 0x8000FFFF, false);
> - }
> + /* Write low address of the ring to C2PMSG_69 */
> + psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
> + WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
> + /* Write high address of the ring to C2PMSG_70 */
> + psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
> + WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
> + /* Write size of ring to C2PMSG_71 */
> + psp_ring_reg = ring->ring_size;
> + WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
> + /* Write the ring initialization command to C2PMSG_64 */
> + psp_ring_reg = ring_type;
> + psp_ring_reg = psp_ring_reg << 16;
> + WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
> +
> + /* Wait for response flag (bit 31) in C2PMSG_64 */
> + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
> + 0x80000000, 0x8000FFFF, false);
>
> return ret;
> }
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] drm/amdgpu: remove re-route ih in psp v12
2025-04-29 10:29 [PATCH 1/2] drm/amdgpu: remove re-route ih in psp v12 Huang Rui
2025-04-29 10:29 ` [PATCH 2/2] drm/amdgpu: cleanup sriov function for " Huang Rui
@ 2025-04-29 13:50 ` Christian König
2025-04-29 14:02 ` Huang Rui
1 sibling, 1 reply; 6+ messages in thread
From: Christian König @ 2025-04-29 13:50 UTC (permalink / raw)
To: Huang Rui, Alex Deucher, Christian König, amd-gfx
Cc: Trigger Huang, Zhu Lingshan
On 4/29/25 12:29, Huang Rui wrote:
> APU doesn't have second IH ring, so re-routing action here is a no-op.
> It will take a lot of time to wait timeout from PSP during the
> initialization. So remove the function in psp v12.
Not 100% sure, but I think this code is also used for non APUs.
So we need to keep it around, just don't try to re-route faults to the second IH ring on APUs.
Regards,
Christian.
>
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/psp_v12_0.c | 34 --------------------------
> 1 file changed, 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
> index 6331941440d9..ed24f61e1ab8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
> @@ -34,9 +34,6 @@
> #include "sdma0/sdma0_4_0_offset.h"
> #include "nbio/nbio_7_4_offset.h"
>
> -#include "oss/osssys_4_0_offset.h"
> -#include "oss/osssys_4_0_sh_mask.h"
> -
> MODULE_FIRMWARE("amdgpu/renoir_asd.bin");
> MODULE_FIRMWARE("amdgpu/renoir_ta.bin");
> MODULE_FIRMWARE("amdgpu/green_sardine_asd.bin");
> @@ -142,35 +139,6 @@ static int psp_v12_0_bootloader_load_sos(struct psp_context *psp)
> return ret;
> }
>
> -static void psp_v12_0_reroute_ih(struct psp_context *psp)
> -{
> - struct amdgpu_device *adev = psp->adev;
> - uint32_t tmp;
> -
> - /* Change IH ring for VMC */
> - tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
> - tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
> - tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
> -
> - WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
> - WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
> - WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
> -
> - psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
> - 0x80000000, 0x8000FFFF, false);
> -
> - /* Change IH ring for UMC */
> - tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
> - tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
> -
> - WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
> - WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
> - WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
> -
> - psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
> - 0x80000000, 0x8000FFFF, false);
> -}
> -
> static int psp_v12_0_ring_create(struct psp_context *psp,
> enum psp_ring_type ring_type)
> {
> @@ -179,8 +147,6 @@ static int psp_v12_0_ring_create(struct psp_context *psp,
> struct psp_ring *ring = &psp->km_ring;
> struct amdgpu_device *adev = psp->adev;
>
> - psp_v12_0_reroute_ih(psp);
> -
> if (amdgpu_sriov_vf(psp->adev)) {
> /* Write low address of the ring to C2PMSG_102 */
> psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] drm/amdgpu: remove re-route ih in psp v12
2025-04-29 13:50 ` [PATCH 1/2] drm/amdgpu: remove re-route ih in " Christian König
@ 2025-04-29 14:02 ` Huang Rui
2025-04-29 14:05 ` Alex Deucher
0 siblings, 1 reply; 6+ messages in thread
From: Huang Rui @ 2025-04-29 14:02 UTC (permalink / raw)
To: Christian König; +Cc: Alex Deucher, amd-gfx, Trigger Huang, Zhu Lingshan
On Tue, Apr 29, 2025 at 03:50:25PM +0200, Christian König wrote:
> On 4/29/25 12:29, Huang Rui wrote:
> > APU doesn't have second IH ring, so re-routing action here is a no-op.
> > It will take a lot of time to wait timeout from PSP during the
> > initialization. So remove the function in psp v12.
>
>
> Not 100% sure, but I think this code is also used for non APUs.
>
> So we need to keep it around, just don't try to re-route faults to the second IH ring on APUs.
Yes, psp v12 is only for APUs like Renoir and related APU kicker and won't
be applied to dGPU. I think we should make series to modify these series to
update re-routing into dGPUs next step.
Thanks,
Ray
>
> Regards,
> Christian.
>
> >
> > Signed-off-by: Huang Rui <ray.huang@amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/psp_v12_0.c | 34 --------------------------
> > 1 file changed, 34 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
> > index 6331941440d9..ed24f61e1ab8 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
> > @@ -34,9 +34,6 @@
> > #include "sdma0/sdma0_4_0_offset.h"
> > #include "nbio/nbio_7_4_offset.h"
> >
> > -#include "oss/osssys_4_0_offset.h"
> > -#include "oss/osssys_4_0_sh_mask.h"
> > -
> > MODULE_FIRMWARE("amdgpu/renoir_asd.bin");
> > MODULE_FIRMWARE("amdgpu/renoir_ta.bin");
> > MODULE_FIRMWARE("amdgpu/green_sardine_asd.bin");
> > @@ -142,35 +139,6 @@ static int psp_v12_0_bootloader_load_sos(struct psp_context *psp)
> > return ret;
> > }
> >
> > -static void psp_v12_0_reroute_ih(struct psp_context *psp)
> > -{
> > - struct amdgpu_device *adev = psp->adev;
> > - uint32_t tmp;
> > -
> > - /* Change IH ring for VMC */
> > - tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
> > - tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
> > - tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
> > -
> > - WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
> > - WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
> > - WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
> > -
> > - psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
> > - 0x80000000, 0x8000FFFF, false);
> > -
> > - /* Change IH ring for UMC */
> > - tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
> > - tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
> > -
> > - WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
> > - WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
> > - WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
> > -
> > - psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
> > - 0x80000000, 0x8000FFFF, false);
> > -}
> > -
> > static int psp_v12_0_ring_create(struct psp_context *psp,
> > enum psp_ring_type ring_type)
> > {
> > @@ -179,8 +147,6 @@ static int psp_v12_0_ring_create(struct psp_context *psp,
> > struct psp_ring *ring = &psp->km_ring;
> > struct amdgpu_device *adev = psp->adev;
> >
> > - psp_v12_0_reroute_ih(psp);
> > -
> > if (amdgpu_sriov_vf(psp->adev)) {
> > /* Write low address of the ring to C2PMSG_102 */
> > psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] drm/amdgpu: remove re-route ih in psp v12
2025-04-29 14:02 ` Huang Rui
@ 2025-04-29 14:05 ` Alex Deucher
0 siblings, 0 replies; 6+ messages in thread
From: Alex Deucher @ 2025-04-29 14:05 UTC (permalink / raw)
To: Huang Rui
Cc: Christian König, Alex Deucher, amd-gfx, Trigger Huang,
Zhu Lingshan
On Tue, Apr 29, 2025 at 10:02 AM Huang Rui <ray.huang@amd.com> wrote:
>
> On Tue, Apr 29, 2025 at 03:50:25PM +0200, Christian König wrote:
> > On 4/29/25 12:29, Huang Rui wrote:
> > > APU doesn't have second IH ring, so re-routing action here is a no-op.
> > > It will take a lot of time to wait timeout from PSP during the
> > > initialization. So remove the function in psp v12.
> >
> >
> > Not 100% sure, but I think this code is also used for non APUs.
> >
> > So we need to keep it around, just don't try to re-route faults to the second IH ring on APUs.
>
> Yes, psp v12 is only for APUs like Renoir and related APU kicker and won't
> be applied to dGPU. I think we should make series to modify these series to
> update re-routing into dGPUs next step.
These functions have been in this file since it was originally added
specifically for APUs. It looks like it was just copy and pasted from
another psp version.
Alex
>
> Thanks,
> Ray
>
> >
> > Regards,
> > Christian.
> >
> > >
> > > Signed-off-by: Huang Rui <ray.huang@amd.com>
> > > ---
> > > drivers/gpu/drm/amd/amdgpu/psp_v12_0.c | 34 --------------------------
> > > 1 file changed, 34 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
> > > index 6331941440d9..ed24f61e1ab8 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
> > > @@ -34,9 +34,6 @@
> > > #include "sdma0/sdma0_4_0_offset.h"
> > > #include "nbio/nbio_7_4_offset.h"
> > >
> > > -#include "oss/osssys_4_0_offset.h"
> > > -#include "oss/osssys_4_0_sh_mask.h"
> > > -
> > > MODULE_FIRMWARE("amdgpu/renoir_asd.bin");
> > > MODULE_FIRMWARE("amdgpu/renoir_ta.bin");
> > > MODULE_FIRMWARE("amdgpu/green_sardine_asd.bin");
> > > @@ -142,35 +139,6 @@ static int psp_v12_0_bootloader_load_sos(struct psp_context *psp)
> > > return ret;
> > > }
> > >
> > > -static void psp_v12_0_reroute_ih(struct psp_context *psp)
> > > -{
> > > - struct amdgpu_device *adev = psp->adev;
> > > - uint32_t tmp;
> > > -
> > > - /* Change IH ring for VMC */
> > > - tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
> > > - tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
> > > - tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
> > > -
> > > - WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
> > > - WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
> > > - WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
> > > -
> > > - psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
> > > - 0x80000000, 0x8000FFFF, false);
> > > -
> > > - /* Change IH ring for UMC */
> > > - tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
> > > - tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
> > > -
> > > - WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
> > > - WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
> > > - WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
> > > -
> > > - psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
> > > - 0x80000000, 0x8000FFFF, false);
> > > -}
> > > -
> > > static int psp_v12_0_ring_create(struct psp_context *psp,
> > > enum psp_ring_type ring_type)
> > > {
> > > @@ -179,8 +147,6 @@ static int psp_v12_0_ring_create(struct psp_context *psp,
> > > struct psp_ring *ring = &psp->km_ring;
> > > struct amdgpu_device *adev = psp->adev;
> > >
> > > - psp_v12_0_reroute_ih(psp);
> > > -
> > > if (amdgpu_sriov_vf(psp->adev)) {
> > > /* Write low address of the ring to C2PMSG_102 */
> > > psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
> >
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2025-04-29 14:05 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-04-29 10:29 [PATCH 1/2] drm/amdgpu: remove re-route ih in psp v12 Huang Rui
2025-04-29 10:29 ` [PATCH 2/2] drm/amdgpu: cleanup sriov function for " Huang Rui
2025-04-29 13:23 ` Alex Deucher
2025-04-29 13:50 ` [PATCH 1/2] drm/amdgpu: remove re-route ih in " Christian König
2025-04-29 14:02 ` Huang Rui
2025-04-29 14:05 ` Alex Deucher
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