* [PATCH 1/1] doc: RISC-V supports semihosting
@ 2025-05-07 4:17 Heinrich Schuchardt
2025-05-08 7:56 ` Leo Liang
2025-05-08 15:15 ` Sean Anderson
0 siblings, 2 replies; 3+ messages in thread
From: Heinrich Schuchardt @ 2025-05-07 4:17 UTC (permalink / raw)
To: Sean Anderson; +Cc: u-boot, Heinrich Schuchardt
Mention that RISC-V supports semihosting.
Update SPDX identifier to current format.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
---
doc/usage/semihosting.rst | 21 ++++++++++++---------
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/doc/usage/semihosting.rst b/doc/usage/semihosting.rst
index 9303a6364d5..dfd6c58222a 100644
--- a/doc/usage/semihosting.rst
+++ b/doc/usage/semihosting.rst
@@ -1,14 +1,17 @@
-.. SPDX-License-Identifier: GPL-2.0+
+.. SPDX-License-Identifier: GPL-2.0-or-later
.. Copyright 2014 Broadcom Corporation.
Semihosting
===========
-Semihosting is ARM's way of having a real or virtual target communicate
-with a host or host debugger for basic operations such as file I/O,
-console I/O, etc. Please see `Arm's semihosting documentation
-<https://developer.arm.com/documentation/100863/latest/>`_ for more
-information.
+Semihosting is a technique to let a real or virtual target communicate with a
+host or host debugger for basic operations such as file I/O, console I/O, etc.
+Originally introduced by ARM it has also been adopted for RISC-V. Please, see
+`Arm's semihosting documentation
+<https://developer.arm.com/documentation/100863/latest/>`_ and
+`RISC-V Semihosting
+<https://drive.google.com/file/d/1qu74D4_EmjGmc03qzfQ7Pf4g6m0fOtcD/view>`_
+for more information.
Platform Support
----------------
@@ -40,7 +43,7 @@ Foundation and Base fastmodel simulators.
QEMU
^^^^
-Another ARM emulator which supports semihosting is `QEMU
+Another emulator which supports semihosting is `QEMU
<https://www.qemu.org/>`_. To enable semihosting, enable
``CONFIG_SERIAL_PROBE_ALL`` when configuring U-Boot, and use
``-semihosting`` when invoking QEMU. Adding ``-nographic`` can also be
@@ -53,8 +56,8 @@ running QEMU, refer to the :doc:`board documentation
OpenOCD
^^^^^^^
-Any ARM platform can use semihosting with an attached debugger. One such
-debugger with good support for a variety of boards and JTAG adapters is
+Any ARM or RISC-V platform can use semihosting with an attached debugger. One
+such debugger with good support for a variety of boards and JTAG adapters is
`OpenOCD <https://openocd.org/>`_. Semihosting is not enabled by default,
so you will need to enable it::
--
2.48.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH 1/1] doc: RISC-V supports semihosting
2025-05-07 4:17 [PATCH 1/1] doc: RISC-V supports semihosting Heinrich Schuchardt
@ 2025-05-08 7:56 ` Leo Liang
2025-05-08 15:15 ` Sean Anderson
1 sibling, 0 replies; 3+ messages in thread
From: Leo Liang @ 2025-05-08 7:56 UTC (permalink / raw)
To: Heinrich Schuchardt; +Cc: Sean Anderson, u-boot
On Wed, May 07, 2025 at 06:17:16AM +0200, Heinrich Schuchardt wrote:
> Mention that RISC-V supports semihosting.
>
> Update SPDX identifier to current format.
>
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
> ---
> doc/usage/semihosting.rst | 21 ++++++++++++---------
> 1 file changed, 12 insertions(+), 9 deletions(-)
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH 1/1] doc: RISC-V supports semihosting
2025-05-07 4:17 [PATCH 1/1] doc: RISC-V supports semihosting Heinrich Schuchardt
2025-05-08 7:56 ` Leo Liang
@ 2025-05-08 15:15 ` Sean Anderson
1 sibling, 0 replies; 3+ messages in thread
From: Sean Anderson @ 2025-05-08 15:15 UTC (permalink / raw)
To: Heinrich Schuchardt; +Cc: u-boot
Hi Heinrich,
On 5/7/25 00:17, Heinrich Schuchardt wrote:
> Mention that RISC-V supports semihosting.
>
> Update SPDX identifier to current format.
>
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
> ---
> doc/usage/semihosting.rst | 21 ++++++++++++---------
> 1 file changed, 12 insertions(+), 9 deletions(-)
>
> diff --git a/doc/usage/semihosting.rst b/doc/usage/semihosting.rst
> index 9303a6364d5..dfd6c58222a 100644
> --- a/doc/usage/semihosting.rst
> +++ b/doc/usage/semihosting.rst
> @@ -1,14 +1,17 @@
> -.. SPDX-License-Identifier: GPL-2.0+
> +.. SPDX-License-Identifier: GPL-2.0-or-later
> .. Copyright 2014 Broadcom Corporation.
>
> Semihosting
> ===========
>
> -Semihosting is ARM's way of having a real or virtual target communicate
> -with a host or host debugger for basic operations such as file I/O,
> -console I/O, etc. Please see `Arm's semihosting documentation
> -<https://cas5-0-urlprotect.trendmicro.com:443/wis/clicktime/v1/query?url=https%3a%2f%2fdeveloper.arm.com%2fdocumentation%2f100863%2flatest%2f&umid=e1d32e91-40f3-412a-84a3-56231fc0ae28&rct=1746591449&auth=d807158c60b7d2502abde8a2fc01f40662980862-c560455b43c648ed3d71f92bb5fc9467eabb905a>`_ for more
> -information.
> +Semihosting is a technique to let a real or virtual target communicate with a
> +host or host debugger for basic operations such as file I/O, console I/O, etc.
> +Originally introduced by ARM it has also been adopted for RISC-V. Please, see
> +`Arm's semihosting documentation
> +<https://cas5-0-urlprotect.trendmicro.com:443/wis/clicktime/v1/query?url=https%3a%2f%2fdeveloper.arm.com%2fdocumentation%2f100863%2flatest%2f&umid=e1d32e91-40f3-412a-84a3-56231fc0ae28&rct=1746591449&auth=d807158c60b7d2502abde8a2fc01f40662980862-c560455b43c648ed3d71f92bb5fc9467eabb905a>`_ and
This link is dead. Can you update it to [1] while you're at it? Thanks.
--Sean
[1] https://github.com/ARM-software/abi-aa/blob/main/semihosting/semihosting.rst
> +`RISC-V Semihosting
> +<https://cas5-0-urlprotect.trendmicro.com:443/wis/clicktime/v1/query?url=https%3a%2f%2fdrive.google.com%2ffile%2fd%2f1qu74D4%5fEmjGmc03qzfQ7Pf4g6m0fOtcD%2fview&umid=e1d32e91-40f3-412a-84a3-56231fc0ae28&rct=1746591449&auth=d807158c60b7d2502abde8a2fc01f40662980862-de1a27031ffe508a9d6a130a34bb51a84ce2447c>`_
> +for more information.
>
> Platform Support
> ----------------
> @@ -40,7 +43,7 @@ Foundation and Base fastmodel simulators.
> QEMU
> ^^^^
>
> -Another ARM emulator which supports semihosting is `QEMU
> +Another emulator which supports semihosting is `QEMU
> <https://cas5-0-urlprotect.trendmicro.com:443/wis/clicktime/v1/query?url=https%3a%2f%2fwww.qemu.org&umid=e1d32e91-40f3-412a-84a3-56231fc0ae28&rct=1746591449&auth=d807158c60b7d2502abde8a2fc01f40662980862-5d24dd3c7adadb856edccd27bd81ab7444841d34>`_. To enable semihosting, enable
> ``CONFIG_SERIAL_PROBE_ALL`` when configuring U-Boot, and use
> ``-semihosting`` when invoking QEMU. Adding ``-nographic`` can also be
> @@ -53,8 +56,8 @@ running QEMU, refer to the :doc:`board documentation
> OpenOCD
> ^^^^^^^
>
> -Any ARM platform can use semihosting with an attached debugger. One such
> -debugger with good support for a variety of boards and JTAG adapters is
> +Any ARM or RISC-V platform can use semihosting with an attached debugger. One
> +such debugger with good support for a variety of boards and JTAG adapters is
> `OpenOCD <https://cas5-0-urlprotect.trendmicro.com:443/wis/clicktime/v1/query?url=https%3a%2f%2fopenocd.org&umid=e1d32e91-40f3-412a-84a3-56231fc0ae28&rct=1746591449&auth=d807158c60b7d2502abde8a2fc01f40662980862-9fa3b9bde769a53933330d7aa1eb430d081756fc>`_. Semihosting is not enabled by default,
> so you will need to enable it::
>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2025-05-08 15:15 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-05-07 4:17 [PATCH 1/1] doc: RISC-V supports semihosting Heinrich Schuchardt
2025-05-08 7:56 ` Leo Liang
2025-05-08 15:15 ` Sean Anderson
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.