From: Yao Zi <ziyao@disroot.org>
To: Jonas Karlman <jonas@kwiboo.se>
Cc: Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Heiko Stuebner <heiko@sntech.de>,
Frank Wang <frank.wang@rock-chips.com>,
Andy Yan <andy.yan@rock-chips.com>,
Cristian Ciocaltea <cristian.ciocaltea@collabora.com>,
Detlev Casanova <detlev.casanova@collabora.com>,
Shresth Prasad <shresthprasad7@gmail.com>,
Chukun Pan <amadeus@jmu.edu.cn>,
linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 5/5] arm64: dts: rockchip: Add naneng-combphy for RK3528
Date: Wed, 21 May 2025 02:27:00 +0000 [thread overview]
Message-ID: <aC059MLlfeUT2a18@pie> (raw)
In-Reply-To: <079c08bc-e8cc-4ed6-a71e-7ef103f635c0@kwiboo.se>
On Tue, May 20, 2025 at 07:51:57PM +0200, Jonas Karlman wrote:
> On 2025-05-19 18:16, Yao Zi wrote:
> > Rockchip RK3528 ships a naneng-combphy that is shared by PCIe and USB
> > 3.0 controllers. Describe it and the pipe-phy grf which it depends on.
> >
> > Signed-off-by: Yao Zi <ziyao@disroot.org>
> > ---
> > arch/arm64/boot/dts/rockchip/rk3528.dtsi | 22 ++++++++++++++++++++++
> > 1 file changed, 22 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> > index b2724c969a76..314afb94e19b 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> > @@ -318,6 +318,11 @@ vpu_grf: syscon@ff340000 {
> > reg = <0x0 0xff340000 0x0 0x8000>;
> > };
> >
> > + pipe_phy_grf: syscon@ff348000 {
> > + compatible = "rockchip,rk3528-pipe-phy-grf", "syscon";
> > + reg = <0x0 0xff348000 0x0 0x8000>;
> > + };
> > +
> > vo_grf: syscon@ff360000 {
> > compatible = "rockchip,rk3528-vo-grf", "syscon";
> > reg = <0x0 0xff360000 0x0 0x10000>;
> > @@ -867,6 +872,23 @@ dmac: dma-controller@ffd60000 {
> > arm,pl330-periph-burst;
> > };
> >
> > + combphy: phy@ffdc0000 {
> > + compatible = "rockchip,rk3528-naneng-combphy";
> > + reg = <0x0 0xffdc0000 0x0 0x10000>;
> > + #phy-cells = <1>;
>
> Should probably be sorted at end or before resets prop.
Will sort the properties.
>
> > + clocks = <&cru CLK_REF_PCIE_INNER_PHY>, <&cru PCLK_PCIE_PHY>,
> This break the ~80 line length limit mostly kept in this file.
Oops, I didn't notice it. Will split them into lines.
> > + <&cru PCLK_PIPE_GRF>;
> > + clock-names = "ref", "apb",
> > + "pipe";
>
> Could be kept on a single line.
>
> > + assigned-clocks = <&cru CLK_REF_PCIE_INNER_PHY>;
> > + assigned-clock-rates = <100000000>;
>
> Other assigned-clock props are sorted before clocks props in this file.
>
> This is also missing power-domains information (also missing from
> dt-bindings patch):
>
> power-domains = <&power RK3528_PD_VPU>;
I didn't expect your power-domain series when writing v1, thanks for the
reminder.
As the power-domain series just came out, I'd like to wait until it
merges and then work further on RK3528 support for naneng-combphy.
I'm not sure whether it's possible to get the combphy cleanup patch (3th
in this series) merged first. It should be ready for merging and I think
this may avoid possible conflicts in the future, Any suggestions will be
appreciated.
> > + resets = <&cru SRST_PCIE_PIPE_PHY>, <&cru SRST_P_PCIE_PHY>;
>
> This also break the ~80 line length limit mostly kept in this file.
I'm willing to keep the ~80 limit and will split the line.
> Regards,
> Jonas
>
> > + reset-names = "phy", "apb";
> > + rockchip,pipe-grf = <&vpu_grf>;
> > + rockchip,pipe-phy-grf = <&pipe_phy_grf>;
> > + status = "disabled";
> > + };
> > +
> > pinctrl: pinctrl {
> > compatible = "rockchip,rk3528-pinctrl";
> > rockchip,grf = <&ioc_grf>;
>
Best regards,
Yao Zi
WARNING: multiple messages have this Message-ID (diff)
From: Yao Zi <ziyao@disroot.org>
To: Jonas Karlman <jonas@kwiboo.se>
Cc: Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Heiko Stuebner <heiko@sntech.de>,
Frank Wang <frank.wang@rock-chips.com>,
Andy Yan <andy.yan@rock-chips.com>,
Cristian Ciocaltea <cristian.ciocaltea@collabora.com>,
Detlev Casanova <detlev.casanova@collabora.com>,
Shresth Prasad <shresthprasad7@gmail.com>,
Chukun Pan <amadeus@jmu.edu.cn>,
linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 5/5] arm64: dts: rockchip: Add naneng-combphy for RK3528
Date: Wed, 21 May 2025 02:27:00 +0000 [thread overview]
Message-ID: <aC059MLlfeUT2a18@pie> (raw)
In-Reply-To: <079c08bc-e8cc-4ed6-a71e-7ef103f635c0@kwiboo.se>
On Tue, May 20, 2025 at 07:51:57PM +0200, Jonas Karlman wrote:
> On 2025-05-19 18:16, Yao Zi wrote:
> > Rockchip RK3528 ships a naneng-combphy that is shared by PCIe and USB
> > 3.0 controllers. Describe it and the pipe-phy grf which it depends on.
> >
> > Signed-off-by: Yao Zi <ziyao@disroot.org>
> > ---
> > arch/arm64/boot/dts/rockchip/rk3528.dtsi | 22 ++++++++++++++++++++++
> > 1 file changed, 22 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> > index b2724c969a76..314afb94e19b 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> > @@ -318,6 +318,11 @@ vpu_grf: syscon@ff340000 {
> > reg = <0x0 0xff340000 0x0 0x8000>;
> > };
> >
> > + pipe_phy_grf: syscon@ff348000 {
> > + compatible = "rockchip,rk3528-pipe-phy-grf", "syscon";
> > + reg = <0x0 0xff348000 0x0 0x8000>;
> > + };
> > +
> > vo_grf: syscon@ff360000 {
> > compatible = "rockchip,rk3528-vo-grf", "syscon";
> > reg = <0x0 0xff360000 0x0 0x10000>;
> > @@ -867,6 +872,23 @@ dmac: dma-controller@ffd60000 {
> > arm,pl330-periph-burst;
> > };
> >
> > + combphy: phy@ffdc0000 {
> > + compatible = "rockchip,rk3528-naneng-combphy";
> > + reg = <0x0 0xffdc0000 0x0 0x10000>;
> > + #phy-cells = <1>;
>
> Should probably be sorted at end or before resets prop.
Will sort the properties.
>
> > + clocks = <&cru CLK_REF_PCIE_INNER_PHY>, <&cru PCLK_PCIE_PHY>,
> This break the ~80 line length limit mostly kept in this file.
Oops, I didn't notice it. Will split them into lines.
> > + <&cru PCLK_PIPE_GRF>;
> > + clock-names = "ref", "apb",
> > + "pipe";
>
> Could be kept on a single line.
>
> > + assigned-clocks = <&cru CLK_REF_PCIE_INNER_PHY>;
> > + assigned-clock-rates = <100000000>;
>
> Other assigned-clock props are sorted before clocks props in this file.
>
> This is also missing power-domains information (also missing from
> dt-bindings patch):
>
> power-domains = <&power RK3528_PD_VPU>;
I didn't expect your power-domain series when writing v1, thanks for the
reminder.
As the power-domain series just came out, I'd like to wait until it
merges and then work further on RK3528 support for naneng-combphy.
I'm not sure whether it's possible to get the combphy cleanup patch (3th
in this series) merged first. It should be ready for merging and I think
this may avoid possible conflicts in the future, Any suggestions will be
appreciated.
> > + resets = <&cru SRST_PCIE_PIPE_PHY>, <&cru SRST_P_PCIE_PHY>;
>
> This also break the ~80 line length limit mostly kept in this file.
I'm willing to keep the ~80 limit and will split the line.
> Regards,
> Jonas
>
> > + reset-names = "phy", "apb";
> > + rockchip,pipe-grf = <&vpu_grf>;
> > + rockchip,pipe-phy-grf = <&pipe_phy_grf>;
> > + status = "disabled";
> > + };
> > +
> > pinctrl: pinctrl {
> > compatible = "rockchip,rk3528-pinctrl";
> > rockchip,grf = <&ioc_grf>;
>
Best regards,
Yao Zi
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
WARNING: multiple messages have this Message-ID (diff)
From: Yao Zi <ziyao@disroot.org>
To: Jonas Karlman <jonas@kwiboo.se>
Cc: Kishon Vijay Abraham I <kishon@kernel.org>,
Rob Herring <robh@kernel.org>, Conor Dooley <conor+dt@kernel.org>,
Heiko Stuebner <heiko@sntech.de>,
Detlev Casanova <detlev.casanova@collabora.com>,
Frank Wang <frank.wang@rock-chips.com>,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-phy@lists.infradead.org,
Shresth Prasad <shresthprasad7@gmail.com>,
Vinod Koul <vkoul@kernel.org>, Chukun Pan <amadeus@jmu.edu.cn>,
linux-arm-kernel@lists.infradead.org,
Andy Yan <andy.yan@rock-chips.com>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
devicetree@vger.kernel.org
Subject: Re: [PATCH v3 5/5] arm64: dts: rockchip: Add naneng-combphy for RK3528
Date: Wed, 21 May 2025 02:27:00 +0000 [thread overview]
Message-ID: <aC059MLlfeUT2a18@pie> (raw)
In-Reply-To: <079c08bc-e8cc-4ed6-a71e-7ef103f635c0@kwiboo.se>
On Tue, May 20, 2025 at 07:51:57PM +0200, Jonas Karlman wrote:
> On 2025-05-19 18:16, Yao Zi wrote:
> > Rockchip RK3528 ships a naneng-combphy that is shared by PCIe and USB
> > 3.0 controllers. Describe it and the pipe-phy grf which it depends on.
> >
> > Signed-off-by: Yao Zi <ziyao@disroot.org>
> > ---
> > arch/arm64/boot/dts/rockchip/rk3528.dtsi | 22 ++++++++++++++++++++++
> > 1 file changed, 22 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> > index b2724c969a76..314afb94e19b 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> > @@ -318,6 +318,11 @@ vpu_grf: syscon@ff340000 {
> > reg = <0x0 0xff340000 0x0 0x8000>;
> > };
> >
> > + pipe_phy_grf: syscon@ff348000 {
> > + compatible = "rockchip,rk3528-pipe-phy-grf", "syscon";
> > + reg = <0x0 0xff348000 0x0 0x8000>;
> > + };
> > +
> > vo_grf: syscon@ff360000 {
> > compatible = "rockchip,rk3528-vo-grf", "syscon";
> > reg = <0x0 0xff360000 0x0 0x10000>;
> > @@ -867,6 +872,23 @@ dmac: dma-controller@ffd60000 {
> > arm,pl330-periph-burst;
> > };
> >
> > + combphy: phy@ffdc0000 {
> > + compatible = "rockchip,rk3528-naneng-combphy";
> > + reg = <0x0 0xffdc0000 0x0 0x10000>;
> > + #phy-cells = <1>;
>
> Should probably be sorted at end or before resets prop.
Will sort the properties.
>
> > + clocks = <&cru CLK_REF_PCIE_INNER_PHY>, <&cru PCLK_PCIE_PHY>,
> This break the ~80 line length limit mostly kept in this file.
Oops, I didn't notice it. Will split them into lines.
> > + <&cru PCLK_PIPE_GRF>;
> > + clock-names = "ref", "apb",
> > + "pipe";
>
> Could be kept on a single line.
>
> > + assigned-clocks = <&cru CLK_REF_PCIE_INNER_PHY>;
> > + assigned-clock-rates = <100000000>;
>
> Other assigned-clock props are sorted before clocks props in this file.
>
> This is also missing power-domains information (also missing from
> dt-bindings patch):
>
> power-domains = <&power RK3528_PD_VPU>;
I didn't expect your power-domain series when writing v1, thanks for the
reminder.
As the power-domain series just came out, I'd like to wait until it
merges and then work further on RK3528 support for naneng-combphy.
I'm not sure whether it's possible to get the combphy cleanup patch (3th
in this series) merged first. It should be ready for merging and I think
this may avoid possible conflicts in the future, Any suggestions will be
appreciated.
> > + resets = <&cru SRST_PCIE_PIPE_PHY>, <&cru SRST_P_PCIE_PHY>;
>
> This also break the ~80 line length limit mostly kept in this file.
I'm willing to keep the ~80 limit and will split the line.
> Regards,
> Jonas
>
> > + reset-names = "phy", "apb";
> > + rockchip,pipe-grf = <&vpu_grf>;
> > + rockchip,pipe-phy-grf = <&pipe_phy_grf>;
> > + status = "disabled";
> > + };
> > +
> > pinctrl: pinctrl {
> > compatible = "rockchip,rk3528-pinctrl";
> > rockchip,grf = <&ioc_grf>;
>
Best regards,
Yao Zi
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
next prev parent reply other threads:[~2025-05-21 2:56 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-19 16:16 [PATCH v3 0/5] Support RK3528 variant of Rockchip naneng-combphy Yao Zi
2025-05-19 16:16 ` Yao Zi
2025-05-19 16:16 ` Yao Zi
2025-05-19 16:16 ` [PATCH v3 1/5] dt-bindings: soc: rockchip: Add RK3528 pipe-phy GRF syscon Yao Zi
2025-05-19 16:16 ` Yao Zi
2025-05-19 16:16 ` Yao Zi
2025-05-19 16:16 ` [PATCH v3 2/5] dt-bindings: phy: rockchip: naneng-combphy: Add RK3528 variant Yao Zi
2025-05-19 16:16 ` Yao Zi
2025-05-19 16:16 ` Yao Zi
2025-05-19 16:39 ` Conor Dooley
2025-05-19 16:39 ` Conor Dooley
2025-05-19 16:39 ` Conor Dooley
2025-05-19 16:16 ` [PATCH v3 3/5] phy: rockchip: naneng-combphy: Add SoC prefix to register definitions Yao Zi
2025-05-19 16:16 ` Yao Zi
2025-05-19 16:16 ` Yao Zi
2025-05-19 19:26 ` Diederik de Haas
2025-05-19 19:26 ` Diederik de Haas
2025-05-19 19:26 ` Diederik de Haas
2025-05-20 3:53 ` Yao Zi
2025-05-20 3:53 ` Yao Zi
2025-05-20 3:53 ` Yao Zi
2025-05-20 7:24 ` neil.armstrong
2025-05-20 7:24 ` neil.armstrong
2025-05-20 7:24 ` neil.armstrong
2025-05-20 8:37 ` Diederik de Haas
2025-05-20 8:37 ` Diederik de Haas
2025-05-20 8:37 ` Diederik de Haas
2025-05-20 11:12 ` Yao Zi
2025-05-20 11:12 ` Yao Zi
2025-05-20 11:12 ` Yao Zi
2025-05-20 11:39 ` Diederik de Haas
2025-05-20 11:39 ` Diederik de Haas
2025-05-20 11:39 ` Diederik de Haas
2025-05-19 16:16 ` [PATCH v3 4/5] phy: rockchip: naneng-combphy: Add RK3528 support Yao Zi
2025-05-19 16:16 ` Yao Zi
2025-05-19 16:16 ` Yao Zi
2025-05-20 7:22 ` neil.armstrong
2025-05-20 7:22 ` neil.armstrong
2025-05-20 7:22 ` neil.armstrong
2025-05-19 16:16 ` [PATCH v3 5/5] arm64: dts: rockchip: Add naneng-combphy for RK3528 Yao Zi
2025-05-19 16:16 ` Yao Zi
2025-05-19 16:16 ` Yao Zi
2025-05-20 17:51 ` Jonas Karlman
2025-05-20 17:51 ` Jonas Karlman
2025-05-20 17:51 ` Jonas Karlman
2025-05-21 2:27 ` Yao Zi [this message]
2025-05-21 2:27 ` Yao Zi
2025-05-21 2:27 ` Yao Zi
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