[PATCH v1 0/6] Introduce support for QCS8300 SoC based IQ8 Series Platform

[PATCH v1 0/6] Introduce support for QCS8300 SoC based IQ8 Series Platform

[Balaji Selvanathan]

These patches introduce the initial support code needed
for the QTI QCS8300 SoC based IQ8 Series Platform.

Please see [1] for SoC related details

Thanks
Balaji

1 - https://docs.qualcomm.com/bundle/publicresource/87-83839-1_REV_A_Qualcomm_IQ8_Series_Product_Brief________.pdf

Balaji Selvanathan (6):
  dt-bindings: power: rpmpd: Add QCS8300 Power Domain Indexes
  dts: qcs8300-ride-u-boot.dtsi: Add memory entry to bootup
  clk/qcom: qcs8300: Add GCC clock driver for QCS8300
  phy: qcom: Enable QMP UFS PHY driver for QCS8300
  qcom_defconfig: Enable QCS8300 clock driver
  configs: add qcs8300_defconfig

 arch/arm/dts/qcs8300-ride-u-boot.dtsi         |  19 +++
 configs/qcom_defconfig                        |   1 +
 configs/qcs8300_defconfig                     |  21 +++
 drivers/clk/qcom/Kconfig                      |   8 +
 drivers/clk/qcom/Makefile                     |   1 +
 drivers/clk/qcom/clock-qcs8300.c              | 146 ++++++++++++++++++
 drivers/phy/qcom/phy-qcom-qmp-ufs.c           |   1 +
 .../include/dt-bindings/power/qcom-rpmpd.h    |  19 +++
 8 files changed, 216 insertions(+)
 create mode 100644 arch/arm/dts/qcs8300-ride-u-boot.dtsi
 create mode 100644 configs/qcs8300_defconfig
 create mode 100644 drivers/clk/qcom/clock-qcs8300.c

-- 
2.34.1

[PATCH v1 1/6] dt-bindings: power: rpmpd: Add QCS8300 Power Domain Indexes

[Balaji Selvanathan]

Added QCS8300 Power Domain Indexes in dt-bindings/power/qcom-rpmhpd.h

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
---
 .../include/dt-bindings/power/qcom-rpmpd.h    | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/dts/upstream/include/dt-bindings/power/qcom-rpmpd.h b/dts/upstream/include/dt-bindings/power/qcom-rpmpd.h
index df599bf4622..50291f918c2 100644
--- a/dts/upstream/include/dt-bindings/power/qcom-rpmpd.h
+++ b/dts/upstream/include/dt-bindings/power/qcom-rpmpd.h
@@ -4,6 +4,25 @@
 #ifndef _DT_BINDINGS_POWER_QCOM_RPMPD_H
 #define _DT_BINDINGS_POWER_QCOM_RPMPD_H
 
+/* QCS8300 Power Domain Indexes */
+#define QCS8300_CX	0
+#define QCS8300_CX_AO	1
+#define QCS8300_DDR	2
+#define QCS8300_EBI	3
+#define QCS8300_GFX	4
+#define QCS8300_LCX	5
+#define QCS8300_LMX	6
+#define QCS8300_MMCX	7
+#define QCS8300_MMCX_AO	8
+#define QCS8300_MSS	9
+#define QCS8300_MX	10
+#define QCS8300_MX_AO	11
+#define QCS8300_MXC	12
+#define QCS8300_MXC_AO	13
+#define QCS8300_NSP0	14
+#define QCS8300_NSP1	15
+#define QCS8300_XO	16
+
 /* SA8775P Power Domain Indexes */
 #define SA8775P_CX	0
 #define SA8775P_CX_AO	1
-- 
2.34.1

[PATCH v1 2/6] dts: qcs8300-ride-u-boot.dtsi: Add memory entry to bootup

[Balaji Selvanathan]

Added the memory entry to bootup.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
---
 arch/arm/dts/qcs8300-ride-u-boot.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
 create mode 100644 arch/arm/dts/qcs8300-ride-u-boot.dtsi

diff --git a/arch/arm/dts/qcs8300-ride-u-boot.dtsi b/arch/arm/dts/qcs8300-ride-u-boot.dtsi
new file mode 100644
index 00000000000..8c353ace71e
--- /dev/null
+++ b/arch/arm/dts/qcs8300-ride-u-boot.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/ {
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x11a80000>,
+		      <0x0 0xc0000000 0x0 0x10000000>,
+		      <0x0 0xd3100000 0x0 0x26b00000>,
+		      <0xe 0x80000000 0x1 0x00000000>,
+		      <0xa 0x80000000 0x1 0x80000000>,
+		      <0x0 0xb0800000 0x0 0x0f200000>,
+		      <0x0 0xd0100000 0x0 0x01800000>,
+		      <0x0 0x91b00000 0x0 0x1e500000>;
+	};
+};
+
-- 
2.34.1

[PATCH v1 3/6] clk/qcom: qcs8300: Add GCC clock driver for QCS8300

[Balaji Selvanathan]

* Port Linux's gcc-qcs8300.c driver to U-Boot for basic bring-up.

* Enable QCS8300 clocks in qcom_defconfig.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
---
 drivers/clk/qcom/Kconfig         |   8 ++
 drivers/clk/qcom/Makefile        |   1 +
 drivers/clk/qcom/clock-qcs8300.c | 146 +++++++++++++++++++++++++++++++
 3 files changed, 155 insertions(+)
 create mode 100644 drivers/clk/qcom/clock-qcs8300.c

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 3ea01f3c969..a226a787af8 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -63,6 +63,14 @@ config CLK_QCOM_SA8775P
 	  on the Snapdragon SA8775 SoC. This driver supports the clocks
 	  and resets exposed by the GCC hardware block.
 
+config CLK_QCOM_QCS8300
+	bool "Qualcomm QCS8300 GCC"
+	select CLK_QCOM
+	help
+	  Say Y here to enable support for the Global Clock Controller
+	  on the Snapdragon QCS8300 SoC. This driver supports the clocks
+	  and resets exposed by the GCC hardware block.
+
 config CLK_QCOM_SDM845
 	bool "Qualcomm SDM845 GCC"
 	select CLK_QCOM
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index e13fc8c1071..7e544bc5407 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_CLK_QCOM_IPQ9574) += clock-ipq9574.o
 obj-$(CONFIG_CLK_QCOM_QCM2290) += clock-qcm2290.o
 obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o
 obj-$(CONFIG_CLK_QCOM_SA8775P) += clock-sa8775p.o
+obj-$(CONFIG_CLK_QCOM_QCS8300) += clock-qcs8300.o
 obj-$(CONFIG_CLK_QCOM_SC7280) += clock-sc7280.o
 obj-$(CONFIG_CLK_QCOM_SM6115) += clock-sm6115.o
 obj-$(CONFIG_CLK_QCOM_SM8150) += clock-sm8150.o
diff --git a/drivers/clk/qcom/clock-qcs8300.c b/drivers/clk/qcom/clock-qcs8300.c
new file mode 100644
index 00000000000..f0b9a0b4fd5
--- /dev/null
+++ b/drivers/clk/qcom/clock-qcs8300.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2024-2025, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ */
+
+#include <linux/types.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+#include <linux/bug.h>
+#include <linux/bitops.h>
+#include <dt-bindings/clock/qcom,qcs8300-gcc.h>
+#include "clock-qcom.h"
+
+#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038
+#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020
+
+static ulong qcs8300_set_rate(struct clk *clk, ulong rate)
+{
+	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+
+	if (clk->id < priv->data->num_clks)
+		debug("%s: %s, requested rate=%ld\n",
+		      __func__, priv->data->clks[clk->id].name, rate);
+
+	switch (clk->id) {
+	case GCC_USB30_PRIM_MOCK_UTMI_CLK:
+		WARN(rate != 19200000, "Unexpected rate for USB30_PRIM_MOCK_UTMI_CLK: %lu\n", rate);
+		clk_rcg_set_rate(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO);
+		return rate;
+	case GCC_USB30_PRIM_MASTER_CLK:
+		WARN(rate != 200000000, "Unexpected rate for USB30_PRIM_MASTER_CLK: %lu\n", rate);
+		clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR,
+				     1, 0, 0, CFG_CLK_SRC_GPLL0_ODD, 8);
+		clk_rcg_set_rate(priv->base, 0xf064, 0, 0);
+		return rate;
+	default:
+		return 0;
+	}
+}
+
+static const struct gate_clk qcs8300_clks[] = {
+	GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x1b088, 1),
+	GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x1b018, 1),
+	GATE_CLK(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0x1b084, 1),
+	GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x1b020, 1),
+	GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x1b024, 1),
+	GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0x1b05c, 1),
+	GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x1b060, 1),
+	GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x83020, 1),
+	GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x83018, 1),
+	GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x830d4, 1),
+	GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x83064, 1),
+};
+
+static int qcs8300_enable(struct clk *clk)
+{
+	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+
+	if (priv->data->num_clks < clk->id) {
+		debug("%s: unknown clk id %lu\n", __func__, clk->id);
+		return 0;
+	}
+
+	debug("%s: clk %ld: %s\n", __func__, clk->id, qcs8300_clks[clk->id].name);
+
+	switch (clk->id) {
+	case GCC_AGGRE_USB3_PRIM_AXI_CLK:
+		qcom_gate_clk_en(priv, GCC_USB30_PRIM_MASTER_CLK);
+		fallthrough;
+	case GCC_USB30_PRIM_MASTER_CLK:
+		qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK);
+		qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK);
+		break;
+	}
+
+	qcom_gate_clk_en(priv, clk->id);
+
+	return 0;
+}
+
+static const struct qcom_reset_map qcs8300_gcc_resets[] = {
+	[GCC_EMAC0_BCR] = { 0xb6000 },
+	[GCC_PCIE_0_BCR] = { 0xa9000 },
+	[GCC_PCIE_0_LINK_DOWN_BCR] = { 0xbf000 },
+	[GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0xbf008 },
+	[GCC_PCIE_0_PHY_BCR] = { 0xa9144 },
+	[GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0xbf00c },
+	[GCC_PCIE_1_BCR] = { 0x77000 },
+	[GCC_PCIE_1_LINK_DOWN_BCR] = { 0xae084 },
+	[GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0xae090 },
+	[GCC_PCIE_1_PHY_BCR] = { 0xae08c },
+	[GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0xae094 },
+	[GCC_SDCC1_BCR] = { 0x20000 },
+	[GCC_UFS_PHY_BCR] = { 0x83000 },
+	[GCC_USB20_PRIM_BCR] = { 0x1c000 },
+	[GCC_USB2_PHY_PRIM_BCR] = { 0x5c01c },
+	[GCC_USB2_PHY_SEC_BCR] = { 0x5c020 },
+	[GCC_USB30_PRIM_BCR] = { 0x1b000 },
+	[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x5c008 },
+	[GCC_USB3_PHY_PRIM_BCR] = { 0x5c000 },
+	[GCC_USB3_PHY_TERT_BCR] = { 0x5c024 },
+	[GCC_USB3_UNIPHY_MP0_BCR] = { 0x5c00c },
+	[GCC_USB3_UNIPHY_MP1_BCR] = { 0x5c010 },
+	[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x5c004 },
+	[GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x5c014 },
+	[GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x5c018 },
+	[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x76000 },
+	[GCC_VIDEO_BCR] = { 0x34000 },
+};
+
+static const struct qcom_power_map qcs8300_gdscs[] = {
+	[GCC_UFS_PHY_GDSC] = { 0x83004 },
+	[GCC_USB30_PRIM_GDSC] = { 0x1B004 },
+};
+
+static struct msm_clk_data qcs8300_gcc_data = {
+	.resets = qcs8300_gcc_resets,
+	.num_resets = ARRAY_SIZE(qcs8300_gcc_resets),
+	.clks = qcs8300_clks,
+	.num_clks = ARRAY_SIZE(qcs8300_clks),
+
+	.power_domains = qcs8300_gdscs,
+	.num_power_domains = ARRAY_SIZE(qcs8300_gdscs),
+
+	.enable = qcs8300_enable,
+	.set_rate = qcs8300_set_rate,
+};
+
+static const struct udevice_id gcc_qcs8300_of_match[] = {
+	{
+		.compatible = "qcom,qcs8300-gcc",
+		.data = (ulong)&qcs8300_gcc_data,
+	},
+	{ }
+};
+
+U_BOOT_DRIVER(gcc_qcs8300) = {
+	.name		= "gcc_qcs8300",
+	.id		= UCLASS_NOP,
+	.of_match	= gcc_qcs8300_of_match,
+	.bind		= qcom_cc_bind,
+	.flags		= DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
+};
-- 
2.34.1

[PATCH v1 4/6] phy: qcom: Enable QMP UFS PHY driver for QCS8300

[Balaji Selvanathan]

Enable QMP phy for QCS8300, referenced from Linux.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
---
 drivers/phy/qcom/phy-qcom-qmp-ufs.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/phy/qcom/phy-qcom-qmp-ufs.c b/drivers/phy/qcom/phy-qcom-qmp-ufs.c
index 449b9767778..18cc665647f 100644
--- a/drivers/phy/qcom/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qcom/phy-qcom-qmp-ufs.c
@@ -1469,6 +1469,7 @@ static const struct udevice_id qmp_ufs_ids[] = {
 	{ .compatible = "qcom,sdm845-qmp-ufs-phy", .data = (ulong)&sdm845_ufsphy_cfg },
 	{ .compatible = "qcom,sm8150-qmp-ufs-phy", .data = (ulong)&sm8150_ufsphy_cfg },
 	{ .compatible = "qcom,sm8250-qmp-ufs-phy", .data = (ulong)&sm8250_ufsphy_cfg },
+	{ .compatible = "qcom,qcs8300-qmp-ufs-phy", .data = (ulong)&sa8775p_ufsphy_cfg },
 	{ .compatible = "qcom,sm8550-qmp-ufs-phy", .data = (ulong)&sm8550_ufsphy_cfg },
 	{ .compatible = "qcom,sm8650-qmp-ufs-phy", .data = (ulong)&sm8650_ufsphy_cfg },
 	{ .compatible = "qcom,sc7280-qmp-ufs-phy", .data = (ulong)&sc7280_ufsphy_cfg, },
-- 
2.34.1

[PATCH v1 5/6] qcom_defconfig: Enable QCS8300 clock driver

[Balaji Selvanathan]

Enable the QCS8300 clock driver in Qualcomm defconfig.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
---
 configs/qcom_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig
index 537806450dc..5a3e5aa8e97 100644
--- a/configs/qcom_defconfig
+++ b/configs/qcom_defconfig
@@ -52,6 +52,7 @@ CONFIG_CLK_QCOM_APQ8096=y
 CONFIG_CLK_QCOM_QCM2290=y
 CONFIG_CLK_QCOM_QCS404=y
 CONFIG_CLK_QCOM_SA8775P=y
+CONFIG_CLK_QCOM_QCS8300=y
 CONFIG_CLK_QCOM_SDM845=y
 CONFIG_CLK_QCOM_SM6115=y
 CONFIG_CLK_QCOM_SM8150=y
-- 
2.34.1

[PATCH v1 6/6] configs: add qcs8300_defconfig

[Balaji Selvanathan]

Introduce a defconfig for QCS8300 based boards.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
---
 configs/qcs8300_defconfig | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
 create mode 100644 configs/qcs8300_defconfig

diff --git a/configs/qcs8300_defconfig b/configs/qcs8300_defconfig
new file mode 100644
index 00000000000..06afc45ec33
--- /dev/null
+++ b/configs/qcs8300_defconfig
@@ -0,0 +1,21 @@
+# Configuration for building U-Boot to be flashed
+# to the uefi partition of QCM6490 dev boards with
+# the "Linux Embedded" partition layout (which have
+# a dedicated "uefi" partition for edk2/U-Boot)
+
+#include "qcom_defconfig"
+
+# Otherwise buildman thinks this isn't an ARM platform
+CONFIG_ARM=y
+
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_BASE=0x99C000
+CONFIG_DEBUG_UART_MSM_GENI=y
+CONFIG_DEBUG_UART_CLOCK=14745600
+
+# Address where U-Boot will be loaded
+CONFIG_TEXT_BASE=0xaf000000
+CONFIG_REMAKE_ELF=y
+
+CONFIG_DEFAULT_DEVICE_TREE="qcom/qcs8300-ride"
-- 
2.34.1

Re: [PATCH v1 0/6] Introduce support for QCS8300 SoC based IQ8 Series Platform

[Casey Connolly]

Hi Balaji,

On 5/8/25 13:19, Balaji Selvanathan wrote:
> These patches introduce the initial support code needed
> for the QTI QCS8300 SoC based IQ8 Series Platform.

Thanks for this series, it's great to see support for this new platform.

Given you're introducing a new defconfig, please update 
doc/board/qualcomm to document how to build and use this platform. We 
missed this with the QCS8100 but I guess they're pretty similar so both 
could be mentioned.

Like we had for the IPQ "RDP" boards, a "Dragonwing" or QCS8xxx document 
which lists the supported boards and build instructions would be awesome.

These docs serve as a good reference for users and an easy way to get 
some idea of what platforms are supported. They should also link to the 
product brief.

Kind regards,

> 
> Please see [1] for SoC related details
> 
> Thanks
> Balaji
> 
> 1 - https://docs.qualcomm.com/bundle/publicresource/87-83839-1_REV_A_Qualcomm_IQ8_Series_Product_Brief________.pdf
> 
> Balaji Selvanathan (6):
>    dt-bindings: power: rpmpd: Add QCS8300 Power Domain Indexes
>    dts: qcs8300-ride-u-boot.dtsi: Add memory entry to bootup
>    clk/qcom: qcs8300: Add GCC clock driver for QCS8300
>    phy: qcom: Enable QMP UFS PHY driver for QCS8300
>    qcom_defconfig: Enable QCS8300 clock driver
>    configs: add qcs8300_defconfig
> 
>   arch/arm/dts/qcs8300-ride-u-boot.dtsi         |  19 +++
>   configs/qcom_defconfig                        |   1 +
>   configs/qcs8300_defconfig                     |  21 +++
>   drivers/clk/qcom/Kconfig                      |   8 +
>   drivers/clk/qcom/Makefile                     |   1 +
>   drivers/clk/qcom/clock-qcs8300.c              | 146 ++++++++++++++++++
>   drivers/phy/qcom/phy-qcom-qmp-ufs.c           |   1 +
>   .../include/dt-bindings/power/qcom-rpmpd.h    |  19 +++
>   8 files changed, 216 insertions(+)
>   create mode 100644 arch/arm/dts/qcs8300-ride-u-boot.dtsi
>   create mode 100644 configs/qcs8300_defconfig
>   create mode 100644 drivers/clk/qcom/clock-qcs8300.c
> 
-- 
Casey (she/they)

Re: [PATCH v1 3/6] clk/qcom: qcs8300: Add GCC clock driver for QCS8300

[Casey Connolly]

On 5/8/25 13:19, Balaji Selvanathan wrote:
> * Port Linux's gcc-qcs8300.c driver to U-Boot for basic bring-up.
> 
> * Enable QCS8300 clocks in qcom_defconfig.
> 
> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
> ---
>   drivers/clk/qcom/Kconfig         |   8 ++
>   drivers/clk/qcom/Makefile        |   1 +
>   drivers/clk/qcom/clock-qcs8300.c | 146 +++++++++++++++++++++++++++++++
>   3 files changed, 155 insertions(+)
>   create mode 100644 drivers/clk/qcom/clock-qcs8300.c
> 
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 3ea01f3c969..a226a787af8 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -63,6 +63,14 @@ config CLK_QCOM_SA8775P
>   	  on the Snapdragon SA8775 SoC. This driver supports the clocks
>   	  and resets exposed by the GCC hardware block.
>   
> +config CLK_QCOM_QCS8300

Alphabetical order please

> +	bool "Qualcomm QCS8300 GCC"
> +	select CLK_QCOM
> +	help
> +	  Say Y here to enable support for the Global Clock Controller
> +	  on the Snapdragon QCS8300 SoC. This driver supports the clocks
> +	  and resets exposed by the GCC hardware block.
> +
>   config CLK_QCOM_SDM845
>   	bool "Qualcomm SDM845 GCC"
>   	select CLK_QCOM
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index e13fc8c1071..7e544bc5407 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -11,6 +11,7 @@ obj-$(CONFIG_CLK_QCOM_IPQ9574) += clock-ipq9574.o
>   obj-$(CONFIG_CLK_QCOM_QCM2290) += clock-qcm2290.o
>   obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o
>   obj-$(CONFIG_CLK_QCOM_SA8775P) += clock-sa8775p.o
> +obj-$(CONFIG_CLK_QCOM_QCS8300) += clock-qcs8300.o

Same here

With that:

Reviewed-by: Casey Connolly <casey.connolly@linaro.org>

>   obj-$(CONFIG_CLK_QCOM_SC7280) += clock-sc7280.o
>   obj-$(CONFIG_CLK_QCOM_SM6115) += clock-sm6115.o
>   obj-$(CONFIG_CLK_QCOM_SM8150) += clock-sm8150.o
> diff --git a/drivers/clk/qcom/clock-qcs8300.c b/drivers/clk/qcom/clock-qcs8300.c
> new file mode 100644
> index 00000000000..f0b9a0b4fd5
> --- /dev/null
> +++ b/drivers/clk/qcom/clock-qcs8300.c
> @@ -0,0 +1,146 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2024-2025, Qualcomm Innovation Center, Inc. All rights reserved.
> + *
> + */
> +
> +#include <linux/types.h>
> +#include <clk-uclass.h>
> +#include <dm.h>
> +#include <linux/delay.h>
> +#include <asm/io.h>
> +#include <linux/bug.h>
> +#include <linux/bitops.h>
> +#include <dt-bindings/clock/qcom,qcs8300-gcc.h>
> +#include "clock-qcom.h"
> +
> +#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038
> +#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020
> +
> +static ulong qcs8300_set_rate(struct clk *clk, ulong rate)
> +{
> +	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
> +
> +	if (clk->id < priv->data->num_clks)
> +		debug("%s: %s, requested rate=%ld\n",
> +		      __func__, priv->data->clks[clk->id].name, rate);
> +
> +	switch (clk->id) {
> +	case GCC_USB30_PRIM_MOCK_UTMI_CLK:
> +		WARN(rate != 19200000, "Unexpected rate for USB30_PRIM_MOCK_UTMI_CLK: %lu\n", rate);
> +		clk_rcg_set_rate(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO);
> +		return rate;
> +	case GCC_USB30_PRIM_MASTER_CLK:
> +		WARN(rate != 200000000, "Unexpected rate for USB30_PRIM_MASTER_CLK: %lu\n", rate);
> +		clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR,
> +				     1, 0, 0, CFG_CLK_SRC_GPLL0_ODD, 8);
> +		clk_rcg_set_rate(priv->base, 0xf064, 0, 0);
> +		return rate;
> +	default:
> +		return 0;
> +	}
> +}
> +
> +static const struct gate_clk qcs8300_clks[] = {
> +	GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x1b088, 1),
> +	GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x1b018, 1),
> +	GATE_CLK(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0x1b084, 1),
> +	GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x1b020, 1),
> +	GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x1b024, 1),
> +	GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0x1b05c, 1),
> +	GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x1b060, 1),
> +	GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x83020, 1),
> +	GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x83018, 1),
> +	GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x830d4, 1),
> +	GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x83064, 1),
> +};
> +
> +static int qcs8300_enable(struct clk *clk)
> +{
> +	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
> +
> +	if (priv->data->num_clks < clk->id) {
> +		debug("%s: unknown clk id %lu\n", __func__, clk->id);
> +		return 0;
> +	}
> +
> +	debug("%s: clk %ld: %s\n", __func__, clk->id, qcs8300_clks[clk->id].name);
> +
> +	switch (clk->id) {
> +	case GCC_AGGRE_USB3_PRIM_AXI_CLK:
> +		qcom_gate_clk_en(priv, GCC_USB30_PRIM_MASTER_CLK);
> +		fallthrough;
> +	case GCC_USB30_PRIM_MASTER_CLK:
> +		qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK);
> +		qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK);
> +		break;
> +	}
> +
> +	qcom_gate_clk_en(priv, clk->id);
> +
> +	return 0;
> +}
> +
> +static const struct qcom_reset_map qcs8300_gcc_resets[] = {
> +	[GCC_EMAC0_BCR] = { 0xb6000 },
> +	[GCC_PCIE_0_BCR] = { 0xa9000 },
> +	[GCC_PCIE_0_LINK_DOWN_BCR] = { 0xbf000 },
> +	[GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0xbf008 },
> +	[GCC_PCIE_0_PHY_BCR] = { 0xa9144 },
> +	[GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0xbf00c },
> +	[GCC_PCIE_1_BCR] = { 0x77000 },
> +	[GCC_PCIE_1_LINK_DOWN_BCR] = { 0xae084 },
> +	[GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0xae090 },
> +	[GCC_PCIE_1_PHY_BCR] = { 0xae08c },
> +	[GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0xae094 },
> +	[GCC_SDCC1_BCR] = { 0x20000 },
> +	[GCC_UFS_PHY_BCR] = { 0x83000 },
> +	[GCC_USB20_PRIM_BCR] = { 0x1c000 },
> +	[GCC_USB2_PHY_PRIM_BCR] = { 0x5c01c },
> +	[GCC_USB2_PHY_SEC_BCR] = { 0x5c020 },
> +	[GCC_USB30_PRIM_BCR] = { 0x1b000 },
> +	[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x5c008 },
> +	[GCC_USB3_PHY_PRIM_BCR] = { 0x5c000 },
> +	[GCC_USB3_PHY_TERT_BCR] = { 0x5c024 },
> +	[GCC_USB3_UNIPHY_MP0_BCR] = { 0x5c00c },
> +	[GCC_USB3_UNIPHY_MP1_BCR] = { 0x5c010 },
> +	[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x5c004 },
> +	[GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x5c014 },
> +	[GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x5c018 },
> +	[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x76000 },
> +	[GCC_VIDEO_BCR] = { 0x34000 },
> +};
> +
> +static const struct qcom_power_map qcs8300_gdscs[] = {
> +	[GCC_UFS_PHY_GDSC] = { 0x83004 },
> +	[GCC_USB30_PRIM_GDSC] = { 0x1B004 },
> +};
> +
> +static struct msm_clk_data qcs8300_gcc_data = {
> +	.resets = qcs8300_gcc_resets,
> +	.num_resets = ARRAY_SIZE(qcs8300_gcc_resets),
> +	.clks = qcs8300_clks,
> +	.num_clks = ARRAY_SIZE(qcs8300_clks),
> +
> +	.power_domains = qcs8300_gdscs,
> +	.num_power_domains = ARRAY_SIZE(qcs8300_gdscs),
> +
> +	.enable = qcs8300_enable,
> +	.set_rate = qcs8300_set_rate,
> +};
> +
> +static const struct udevice_id gcc_qcs8300_of_match[] = {
> +	{
> +		.compatible = "qcom,qcs8300-gcc",
> +		.data = (ulong)&qcs8300_gcc_data,
> +	},
> +	{ }
> +};
> +
> +U_BOOT_DRIVER(gcc_qcs8300) = {
> +	.name		= "gcc_qcs8300",
> +	.id		= UCLASS_NOP,
> +	.of_match	= gcc_qcs8300_of_match,
> +	.bind		= qcom_cc_bind,
> +	.flags		= DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
> +};

-- 
Casey (she/they)

Re: [PATCH v1 4/6] phy: qcom: Enable QMP UFS PHY driver for QCS8300

[Casey Connolly]

On 5/8/25 13:19, Balaji Selvanathan wrote:
> Enable QMP phy for QCS8300, referenced from Linux.
> 
> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>

Reviewed-by: Casey Connolly <casey.connolly@linaro.org>> ---
>   drivers/phy/qcom/phy-qcom-qmp-ufs.c | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/phy/qcom/phy-qcom-qmp-ufs.c b/drivers/phy/qcom/phy-qcom-qmp-ufs.c
> index 449b9767778..18cc665647f 100644
> --- a/drivers/phy/qcom/phy-qcom-qmp-ufs.c
> +++ b/drivers/phy/qcom/phy-qcom-qmp-ufs.c
> @@ -1469,6 +1469,7 @@ static const struct udevice_id qmp_ufs_ids[] = {
>   	{ .compatible = "qcom,sdm845-qmp-ufs-phy", .data = (ulong)&sdm845_ufsphy_cfg },
>   	{ .compatible = "qcom,sm8150-qmp-ufs-phy", .data = (ulong)&sm8150_ufsphy_cfg },
>   	{ .compatible = "qcom,sm8250-qmp-ufs-phy", .data = (ulong)&sm8250_ufsphy_cfg },
> +	{ .compatible = "qcom,qcs8300-qmp-ufs-phy", .data = (ulong)&sa8775p_ufsphy_cfg },
>   	{ .compatible = "qcom,sm8550-qmp-ufs-phy", .data = (ulong)&sm8550_ufsphy_cfg },
>   	{ .compatible = "qcom,sm8650-qmp-ufs-phy", .data = (ulong)&sm8650_ufsphy_cfg },
>   	{ .compatible = "qcom,sc7280-qmp-ufs-phy", .data = (ulong)&sc7280_ufsphy_cfg, },

-- 
Casey (she/they)

Re: [PATCH v1 5/6] qcom_defconfig: Enable QCS8300 clock driver

[Casey Connolly]

On 5/8/25 13:19, Balaji Selvanathan wrote:
> Enable the QCS8300 clock driver in Qualcomm defconfig.
> 
> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
> ---
>   configs/qcom_defconfig | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig
> index 537806450dc..5a3e5aa8e97 100644
> --- a/configs/qcom_defconfig
> +++ b/configs/qcom_defconfig
> @@ -52,6 +52,7 @@ CONFIG_CLK_QCOM_APQ8096=y
>   CONFIG_CLK_QCOM_QCM2290=y
>   CONFIG_CLK_QCOM_QCS404=y
>   CONFIG_CLK_QCOM_SA8775P=y
> +CONFIG_CLK_QCOM_QCS8300=y

Please run "make qcom_defconfig && make savedefconfig && cp defconfig 
configs/qcom_defconfig"

It's fine if there's some other changes. But this needs to be in the 
right order.

With that

Reviewed-by: Casey Connolly <casey.connolly@linaro.org>

>   CONFIG_CLK_QCOM_SDM845=y
>   CONFIG_CLK_QCOM_SM6115=y
>   CONFIG_CLK_QCOM_SM8150=y
-- 
Casey (she/they)

Re: [PATCH v1 6/6] configs: add qcs8300_defconfig

[Casey Connolly]

On 5/8/25 13:19, Balaji Selvanathan wrote:
> Introduce a defconfig for QCS8300 based boards.
> 
> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
> ---
>   configs/qcs8300_defconfig | 21 +++++++++++++++++++++
>   1 file changed, 21 insertions(+)
>   create mode 100644 configs/qcs8300_defconfig
> 
> diff --git a/configs/qcs8300_defconfig b/configs/qcs8300_defconfig
> new file mode 100644
> index 00000000000..06afc45ec33
> --- /dev/null
> +++ b/configs/qcs8300_defconfig
> @@ -0,0 +1,21 @@
> +# Configuration for building U-Boot to be flashed
> +# to the uefi partition of QCM6490 dev boards with

I don't think so

> +# the "Linux Embedded" partition layout (which have
> +# a dedicated "uefi" partition for edk2/U-Boot)
> +
> +#include "qcom_defconfig"
> +
> +# Otherwise buildman thinks this isn't an ARM platform
> +CONFIG_ARM=y
> +
> +CONFIG_DEBUG_UART=y
> +CONFIG_DEBUG_UART_ANNOUNCE=y
> +CONFIG_DEBUG_UART_BASE=0x99C000
> +CONFIG_DEBUG_UART_MSM_GENI=y
> +CONFIG_DEBUG_UART_CLOCK=14745600
> +
> +# Address where U-Boot will be loaded
> +CONFIG_TEXT_BASE=0xaf000000
> +CONFIG_REMAKE_ELF=y
> +
> +CONFIG_DEFAULT_DEVICE_TREE="qcom/qcs8300-ride"

-- 
Casey (she/they)

Re: [PATCH v1 2/6] dts: qcs8300-ride-u-boot.dtsi: Add memory entry to bootup

[Casey Connolly]

On 5/8/25 13:19, Balaji Selvanathan wrote:
> Added the memory entry to bootup.
> 
> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>

Woof we need to get the SMEM parsing sorted...

Reviewed-by: Casey Connolly <casey.connolly@linaro.org>

> ---
>   arch/arm/dts/qcs8300-ride-u-boot.dtsi | 19 +++++++++++++++++++
>   1 file changed, 19 insertions(+)
>   create mode 100644 arch/arm/dts/qcs8300-ride-u-boot.dtsi
> 
> diff --git a/arch/arm/dts/qcs8300-ride-u-boot.dtsi b/arch/arm/dts/qcs8300-ride-u-boot.dtsi
> new file mode 100644
> index 00000000000..8c353ace71e
> --- /dev/null
> +++ b/arch/arm/dts/qcs8300-ride-u-boot.dtsi
> @@ -0,0 +1,19 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +/ {
> +	memory@80000000 {
> +		device_type = "memory";
> +		reg = <0x0 0x80000000 0x0 0x11a80000>,
> +		      <0x0 0xc0000000 0x0 0x10000000>,
> +		      <0x0 0xd3100000 0x0 0x26b00000>,
> +		      <0xe 0x80000000 0x1 0x00000000>,
> +		      <0xa 0x80000000 0x1 0x80000000>,
> +		      <0x0 0xb0800000 0x0 0x0f200000>,
> +		      <0x0 0xd0100000 0x0 0x01800000>,
> +		      <0x0 0x91b00000 0x0 0x1e500000>;
> +	};
> +};
> +
-- 
Casey (she/they)

Re: [PATCH v1 6/6] configs: add qcs8300_defconfig

[Casey Connolly]

Hi Balaji,

On 5/8/25 13:19, Balaji Selvanathan wrote:
> Introduce a defconfig for QCS8300 based boards.
> 
> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
> ---
>   configs/qcs8300_defconfig | 21 +++++++++++++++++++++
>   1 file changed, 21 insertions(+)
>   create mode 100644 configs/qcs8300_defconfig
> 
> diff --git a/configs/qcs8300_defconfig b/configs/qcs8300_defconfig
> new file mode 100644
> index 00000000000..06afc45ec33
> --- /dev/null
> +++ b/configs/qcs8300_defconfig

Also, this should be named qcom_qcs8300_defconfig so that 
get_maintainers will work properly.

Kind regards,

> @@ -0,0 +1,21 @@
> +# Configuration for building U-Boot to be flashed
> +# to the uefi partition of QCM6490 dev boards with
> +# the "Linux Embedded" partition layout (which have
> +# a dedicated "uefi" partition for edk2/U-Boot)
> +
> +#include "qcom_defconfig"
> +
> +# Otherwise buildman thinks this isn't an ARM platform
> +CONFIG_ARM=y
> +
> +CONFIG_DEBUG_UART=y
> +CONFIG_DEBUG_UART_ANNOUNCE=y
> +CONFIG_DEBUG_UART_BASE=0x99C000
> +CONFIG_DEBUG_UART_MSM_GENI=y
> +CONFIG_DEBUG_UART_CLOCK=14745600
> +
> +# Address where U-Boot will be loaded
> +CONFIG_TEXT_BASE=0xaf000000
> +CONFIG_REMAKE_ELF=y
> +
> +CONFIG_DEFAULT_DEVICE_TREE="qcom/qcs8300-ride"

-- 
Casey (she/they)

Re: [PATCH v1 1/6] dt-bindings: power: rpmpd: Add QCS8300 Power Domain Indexes

[Sumit Garg]

Hi Balaji,

On Thu, May 08, 2025 at 04:49:47PM +0530, Balaji Selvanathan wrote:
> Added QCS8300 Power Domain Indexes in dt-bindings/power/qcom-rpmhpd.h
> 
> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
> ---
>  .../include/dt-bindings/power/qcom-rpmpd.h    | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
> 
> diff --git a/dts/upstream/include/dt-bindings/power/qcom-rpmpd.h b/dts/upstream/include/dt-bindings/power/qcom-rpmpd.h
> index df599bf4622..50291f918c2 100644
> --- a/dts/upstream/include/dt-bindings/power/qcom-rpmpd.h
> +++ b/dts/upstream/include/dt-bindings/power/qcom-rpmpd.h

Please don't directly patch dts/upstream subtree. Rather you should
follow documentation here [1] as to how you can cherry pick patches from
upstream dt-rebasing tree.

Also, are these DT bindings header changes posted in Linux kernel
upstream?

[1] https://docs.u-boot.org/en/latest/develop/devicetree/control.html#resyncing-with-devicetree-rebasing

-Sumit

> @@ -4,6 +4,25 @@
>  #ifndef _DT_BINDINGS_POWER_QCOM_RPMPD_H
>  #define _DT_BINDINGS_POWER_QCOM_RPMPD_H
>  
> +/* QCS8300 Power Domain Indexes */
> +#define QCS8300_CX	0
> +#define QCS8300_CX_AO	1
> +#define QCS8300_DDR	2
> +#define QCS8300_EBI	3
> +#define QCS8300_GFX	4
> +#define QCS8300_LCX	5
> +#define QCS8300_LMX	6
> +#define QCS8300_MMCX	7
> +#define QCS8300_MMCX_AO	8
> +#define QCS8300_MSS	9
> +#define QCS8300_MX	10
> +#define QCS8300_MX_AO	11
> +#define QCS8300_MXC	12
> +#define QCS8300_MXC_AO	13
> +#define QCS8300_NSP0	14
> +#define QCS8300_NSP1	15
> +#define QCS8300_XO	16
> +
>  /* SA8775P Power Domain Indexes */
>  #define SA8775P_CX	0
>  #define SA8775P_CX_AO	1
> -- 
> 2.34.1
>