From: Charlie Jenkins <charlie@rivosinc.com>
To: "Clément Léger" <cleger@rivosinc.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Shuah Khan <shuah@kernel.org>, Jonathan Corbet <corbet@lwn.net>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org, kvm@vger.kernel.org,
kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org,
Samuel Holland <samuel.holland@sifive.com>,
Andrew Jones <ajones@ventanamicro.com>,
Deepak Gupta <debug@rivosinc.com>
Subject: Re: [PATCH v7 09/14] riscv: misaligned: move emulated access uniformity check in a function
Date: Mon, 19 May 2025 16:32:01 -0700 [thread overview]
Message-ID: <aCu_ce-kVQsyjrh5@ghost> (raw)
In-Reply-To: <20250515082217.433227-10-cleger@rivosinc.com>
On Thu, May 15, 2025 at 10:22:10AM +0200, Clément Léger wrote:
> Split the code that check for the uniformity of misaligned accesses
> performance on all cpus from check_unaligned_access_emulated_all_cpus()
> to its own function which will be used for delegation check. No
> functional changes intended.
>
> Signed-off-by: Clément Léger <cleger@rivosinc.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> ---
> arch/riscv/kernel/traps_misaligned.c | 20 ++++++++++++++------
> 1 file changed, 14 insertions(+), 6 deletions(-)
>
> diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
> index e551ba17f557..287ec37021c8 100644
> --- a/arch/riscv/kernel/traps_misaligned.c
> +++ b/arch/riscv/kernel/traps_misaligned.c
> @@ -647,6 +647,18 @@ bool __init check_vector_unaligned_access_emulated_all_cpus(void)
> }
> #endif
>
> +static bool all_cpus_unaligned_scalar_access_emulated(void)
> +{
> + int cpu;
> +
> + for_each_online_cpu(cpu)
> + if (per_cpu(misaligned_access_speed, cpu) !=
misaligned_access_speed is only defined when
CONFIG_RISCV_SCALAR_MISALIGNED. This function should return false when
!CONFIG_RISCV_SCALAR_MISALIGNED and only use this logic otherwise.
- Charlie
> + RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED)
> + return false;
> +
> + return true;
> +}
> +
> #ifdef CONFIG_RISCV_SCALAR_MISALIGNED
>
> static bool unaligned_ctl __read_mostly;
> @@ -685,8 +697,6 @@ static int cpu_online_check_unaligned_access_emulated(unsigned int cpu)
>
> bool __init check_unaligned_access_emulated_all_cpus(void)
> {
> - int cpu;
> -
> /*
> * We can only support PR_UNALIGN controls if all CPUs have misaligned
> * accesses emulated since tasks requesting such control can run on any
> @@ -694,10 +704,8 @@ bool __init check_unaligned_access_emulated_all_cpus(void)
> */
> on_each_cpu(check_unaligned_access_emulated, NULL, 1);
>
> - for_each_online_cpu(cpu)
> - if (per_cpu(misaligned_access_speed, cpu)
> - != RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED)
> - return false;
> + if (!all_cpus_unaligned_scalar_access_emulated())
> + return false;
>
> unaligned_ctl = true;
> return true;
> --
> 2.49.0
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
--
kvm-riscv mailing list
kvm-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/kvm-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Charlie Jenkins <charlie@rivosinc.com>
To: "Clément Léger" <cleger@rivosinc.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Shuah Khan <shuah@kernel.org>, Jonathan Corbet <corbet@lwn.net>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org, kvm@vger.kernel.org,
kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org,
Samuel Holland <samuel.holland@sifive.com>,
Andrew Jones <ajones@ventanamicro.com>,
Deepak Gupta <debug@rivosinc.com>
Subject: Re: [PATCH v7 09/14] riscv: misaligned: move emulated access uniformity check in a function
Date: Mon, 19 May 2025 16:32:01 -0700 [thread overview]
Message-ID: <aCu_ce-kVQsyjrh5@ghost> (raw)
In-Reply-To: <20250515082217.433227-10-cleger@rivosinc.com>
On Thu, May 15, 2025 at 10:22:10AM +0200, Clément Léger wrote:
> Split the code that check for the uniformity of misaligned accesses
> performance on all cpus from check_unaligned_access_emulated_all_cpus()
> to its own function which will be used for delegation check. No
> functional changes intended.
>
> Signed-off-by: Clément Léger <cleger@rivosinc.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> ---
> arch/riscv/kernel/traps_misaligned.c | 20 ++++++++++++++------
> 1 file changed, 14 insertions(+), 6 deletions(-)
>
> diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
> index e551ba17f557..287ec37021c8 100644
> --- a/arch/riscv/kernel/traps_misaligned.c
> +++ b/arch/riscv/kernel/traps_misaligned.c
> @@ -647,6 +647,18 @@ bool __init check_vector_unaligned_access_emulated_all_cpus(void)
> }
> #endif
>
> +static bool all_cpus_unaligned_scalar_access_emulated(void)
> +{
> + int cpu;
> +
> + for_each_online_cpu(cpu)
> + if (per_cpu(misaligned_access_speed, cpu) !=
misaligned_access_speed is only defined when
CONFIG_RISCV_SCALAR_MISALIGNED. This function should return false when
!CONFIG_RISCV_SCALAR_MISALIGNED and only use this logic otherwise.
- Charlie
> + RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED)
> + return false;
> +
> + return true;
> +}
> +
> #ifdef CONFIG_RISCV_SCALAR_MISALIGNED
>
> static bool unaligned_ctl __read_mostly;
> @@ -685,8 +697,6 @@ static int cpu_online_check_unaligned_access_emulated(unsigned int cpu)
>
> bool __init check_unaligned_access_emulated_all_cpus(void)
> {
> - int cpu;
> -
> /*
> * We can only support PR_UNALIGN controls if all CPUs have misaligned
> * accesses emulated since tasks requesting such control can run on any
> @@ -694,10 +704,8 @@ bool __init check_unaligned_access_emulated_all_cpus(void)
> */
> on_each_cpu(check_unaligned_access_emulated, NULL, 1);
>
> - for_each_online_cpu(cpu)
> - if (per_cpu(misaligned_access_speed, cpu)
> - != RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED)
> - return false;
> + if (!all_cpus_unaligned_scalar_access_emulated())
> + return false;
>
> unaligned_ctl = true;
> return true;
> --
> 2.49.0
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Charlie Jenkins <charlie@rivosinc.com>
To: "Clément Léger" <cleger@rivosinc.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Shuah Khan <shuah@kernel.org>, Jonathan Corbet <corbet@lwn.net>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org, kvm@vger.kernel.org,
kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org,
Samuel Holland <samuel.holland@sifive.com>,
Andrew Jones <ajones@ventanamicro.com>,
Deepak Gupta <debug@rivosinc.com>
Subject: Re: [PATCH v7 09/14] riscv: misaligned: move emulated access uniformity check in a function
Date: Mon, 19 May 2025 16:32:01 -0700 [thread overview]
Message-ID: <aCu_ce-kVQsyjrh5@ghost> (raw)
In-Reply-To: <20250515082217.433227-10-cleger@rivosinc.com>
On Thu, May 15, 2025 at 10:22:10AM +0200, Clément Léger wrote:
> Split the code that check for the uniformity of misaligned accesses
> performance on all cpus from check_unaligned_access_emulated_all_cpus()
> to its own function which will be used for delegation check. No
> functional changes intended.
>
> Signed-off-by: Clément Léger <cleger@rivosinc.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> ---
> arch/riscv/kernel/traps_misaligned.c | 20 ++++++++++++++------
> 1 file changed, 14 insertions(+), 6 deletions(-)
>
> diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
> index e551ba17f557..287ec37021c8 100644
> --- a/arch/riscv/kernel/traps_misaligned.c
> +++ b/arch/riscv/kernel/traps_misaligned.c
> @@ -647,6 +647,18 @@ bool __init check_vector_unaligned_access_emulated_all_cpus(void)
> }
> #endif
>
> +static bool all_cpus_unaligned_scalar_access_emulated(void)
> +{
> + int cpu;
> +
> + for_each_online_cpu(cpu)
> + if (per_cpu(misaligned_access_speed, cpu) !=
misaligned_access_speed is only defined when
CONFIG_RISCV_SCALAR_MISALIGNED. This function should return false when
!CONFIG_RISCV_SCALAR_MISALIGNED and only use this logic otherwise.
- Charlie
> + RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED)
> + return false;
> +
> + return true;
> +}
> +
> #ifdef CONFIG_RISCV_SCALAR_MISALIGNED
>
> static bool unaligned_ctl __read_mostly;
> @@ -685,8 +697,6 @@ static int cpu_online_check_unaligned_access_emulated(unsigned int cpu)
>
> bool __init check_unaligned_access_emulated_all_cpus(void)
> {
> - int cpu;
> -
> /*
> * We can only support PR_UNALIGN controls if all CPUs have misaligned
> * accesses emulated since tasks requesting such control can run on any
> @@ -694,10 +704,8 @@ bool __init check_unaligned_access_emulated_all_cpus(void)
> */
> on_each_cpu(check_unaligned_access_emulated, NULL, 1);
>
> - for_each_online_cpu(cpu)
> - if (per_cpu(misaligned_access_speed, cpu)
> - != RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED)
> - return false;
> + if (!all_cpus_unaligned_scalar_access_emulated())
> + return false;
>
> unaligned_ctl = true;
> return true;
> --
> 2.49.0
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2025-05-19 23:32 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-15 8:22 [PATCH v7 00/14] riscv: add SBI FWFT misaligned exception delegation support Clément Léger
2025-05-15 8:22 ` Clément Léger
2025-05-15 8:22 ` Clément Léger
2025-05-15 8:22 ` [PATCH v7 01/14] riscv: sbi: add Firmware Feature (FWFT) SBI extensions definitions Clément Léger
2025-05-15 8:22 ` Clément Léger
2025-05-15 8:22 ` Clément Léger
2025-05-15 8:22 ` [PATCH v7 02/14] riscv: sbi: remove useless parenthesis Clément Léger
2025-05-15 8:22 ` Clément Léger
2025-05-15 8:22 ` Clément Léger
2025-05-15 8:22 ` [PATCH v7 03/14] riscv: sbi: add new SBI error mappings Clément Léger
2025-05-15 8:22 ` Clément Léger
2025-05-15 8:22 ` Clément Léger
2025-05-15 8:22 ` [PATCH v7 04/14] riscv: sbi: add FWFT extension interface Clément Léger
2025-05-15 8:22 ` Clément Léger
2025-05-15 8:22 ` Clément Léger
2025-05-15 8:22 ` [PATCH v7 05/14] riscv: sbi: add SBI FWFT extension calls Clément Léger
2025-05-15 8:22 ` Clément Léger
2025-05-15 8:22 ` Clément Léger
2025-05-15 8:22 ` [PATCH v7 06/14] riscv: misaligned: request misaligned exception from SBI Clément Léger
2025-05-15 8:22 ` Clément Léger
2025-05-15 8:22 ` Clément Léger
2025-05-15 8:22 ` [PATCH v7 07/14] riscv: misaligned: use on_each_cpu() for scalar misaligned access probing Clément Léger
2025-05-15 8:22 ` Clément Léger
2025-05-15 8:22 ` Clément Léger
2025-05-15 8:22 ` [PATCH v7 08/14] riscv: misaligned: use correct CONFIG_ ifdef for misaligned_access_speed Clément Léger
2025-05-15 8:22 ` Clément Léger
2025-05-15 8:22 ` Clément Léger
2025-05-15 8:22 ` [PATCH v7 09/14] riscv: misaligned: move emulated access uniformity check in a function Clément Léger
2025-05-15 8:22 ` Clément Léger
2025-05-15 8:22 ` Clément Léger
2025-05-19 23:32 ` Charlie Jenkins [this message]
2025-05-19 23:32 ` Charlie Jenkins
2025-05-19 23:32 ` Charlie Jenkins
2025-05-20 8:19 ` Clément Léger
2025-05-20 8:19 ` Clément Léger
2025-05-20 8:19 ` Clément Léger
2025-05-20 17:08 ` Charlie Jenkins
2025-05-20 17:08 ` Charlie Jenkins
2025-05-20 17:08 ` Charlie Jenkins
2025-05-22 6:49 ` Clément Léger
2025-05-22 6:49 ` Clément Léger
2025-05-22 6:49 ` Clément Léger
2025-05-15 8:22 ` [PATCH v7 10/14] riscv: misaligned: add a function to check misalign trap delegability Clément Léger
2025-05-15 8:22 ` Clément Léger
2025-05-15 8:22 ` Clément Léger
2025-05-15 8:22 ` [PATCH v7 11/14] RISC-V: KVM: add SBI extension init()/deinit() functions Clément Léger
2025-05-15 8:22 ` Clément Léger
2025-05-15 8:22 ` Clément Léger
2025-05-15 8:22 ` [PATCH v7 12/14] RISC-V: KVM: add SBI extension reset callback Clément Léger
2025-05-15 8:22 ` Clément Léger
2025-05-15 8:22 ` Clément Léger
2025-05-15 8:22 ` [PATCH v7 13/14] RISC-V: KVM: add support for FWFT SBI extension Clément Léger
2025-05-15 8:22 ` Clément Léger
2025-05-15 8:22 ` Clément Léger
2025-05-15 8:22 ` [PATCH v7 14/14] RISC-V: KVM: add support for SBI_FWFT_MISALIGNED_DELEG Clément Léger
2025-05-15 8:22 ` Clément Léger
2025-05-15 8:22 ` Clément Léger
2025-05-16 23:57 ` Atish Patra
2025-05-16 23:57 ` Atish Patra
2025-05-16 23:57 ` Atish Patra
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