[PATCH 1/1] configs: raise SPL_SYS_MALLOC_SIZE to 8 MiB on RISC-V

[PATCH 1/1] configs: raise SPL_SYS_MALLOC_SIZE to 8 MiB on RISC-V

[Heinrich Schuchardt]

On several RISC-V boards we have seen that 1 MiB is a insufficient value
for CONFIG_SPL_SYS_MALLOC_SIZE.

For instance qemu-riscv32_spl_defconfig fails booting because u-boot.itb
exceeds 1 MiB.

8 MiB is a reasonable value that allows adding FPGA blobs or splash images
to main U-boot.

Reported-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
---
 common/spl/Kconfig                     | 2 +-
 configs/starfive_visionfive2_defconfig | 1 -
 configs/th1520_lpi4a_defconfig         | 1 -
 configs/xilinx_mbv32_defconfig         | 1 -
 configs/xilinx_mbv32_smode_defconfig   | 1 -
 configs/xilinx_mbv64_defconfig         | 1 -
 configs/xilinx_mbv64_smode_defconfig   | 1 -
 7 files changed, 1 insertion(+), 7 deletions(-)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 77cf04d38ed..a12f030daed 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -488,7 +488,7 @@ config SPL_CUSTOM_SYS_MALLOC_ADDR
 config SPL_SYS_MALLOC_SIZE
 	hex "Size of the SPL malloc pool"
 	depends on SPL_SYS_MALLOC
-	default 0x180000 if BIOSEMU && RISCV
+	default 0x800000 if RISCV
 	default 0x100000
 
 config SPL_READ_ONLY
diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig
index e145ced8db8..6982d422a82 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -56,7 +56,6 @@ CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80000000
-CONFIG_SPL_SYS_MALLOC_SIZE=0x400000
 CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2
diff --git a/configs/th1520_lpi4a_defconfig b/configs/th1520_lpi4a_defconfig
index b19dc009fde..6ced7afe6b1 100644
--- a/configs/th1520_lpi4a_defconfig
+++ b/configs/th1520_lpi4a_defconfig
@@ -107,4 +107,3 @@ CONFIG_SPL_MMC_y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x10000000
-CONFIG_SPL_SYS_MALLOC_SIZE=0x400000
diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig
index 861d1475453..c3f33d6454d 100644
--- a/configs/xilinx_mbv32_defconfig
+++ b/configs/xilinx_mbv32_defconfig
@@ -29,7 +29,6 @@ CONFIG_SPL_MAX_SIZE=0x40000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
 # CONFIG_CMD_MII is not set
 CONFIG_CMD_TIMER=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
diff --git a/configs/xilinx_mbv32_smode_defconfig b/configs/xilinx_mbv32_smode_defconfig
index 9398b4c240d..c588bd563ac 100644
--- a/configs/xilinx_mbv32_smode_defconfig
+++ b/configs/xilinx_mbv32_smode_defconfig
@@ -30,7 +30,6 @@ CONFIG_SPL_MAX_SIZE=0x40000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
 CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x2
 # CONFIG_CMD_MII is not set
 CONFIG_CMD_TIMER=y
diff --git a/configs/xilinx_mbv64_defconfig b/configs/xilinx_mbv64_defconfig
index c39925bd86a..c2c677d7443 100644
--- a/configs/xilinx_mbv64_defconfig
+++ b/configs/xilinx_mbv64_defconfig
@@ -30,7 +30,6 @@ CONFIG_SPL_MAX_SIZE=0x40000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
 # CONFIG_CMD_MII is not set
 CONFIG_CMD_TIMER=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
diff --git a/configs/xilinx_mbv64_smode_defconfig b/configs/xilinx_mbv64_smode_defconfig
index 811f93a2671..7a26c85dfb7 100644
--- a/configs/xilinx_mbv64_smode_defconfig
+++ b/configs/xilinx_mbv64_smode_defconfig
@@ -31,7 +31,6 @@ CONFIG_SPL_MAX_SIZE=0x40000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
 CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x2
 # CONFIG_CMD_MII is not set
 CONFIG_CMD_TIMER=y
-- 
2.48.1

Re: [PATCH 1/1] configs: raise SPL_SYS_MALLOC_SIZE to 8 MiB on RISC-V

[Leo Liang]

On Sun, May 25, 2025 at 12:42:48PM +0200, Heinrich Schuchardt wrote:
> [EXTERNAL MAIL]
> 
> On several RISC-V boards we have seen that 1 MiB is a insufficient value
> for CONFIG_SPL_SYS_MALLOC_SIZE.
> 
> For instance qemu-riscv32_spl_defconfig fails booting because u-boot.itb
> exceeds 1 MiB.
> 
> 8 MiB is a reasonable value that allows adding FPGA blobs or splash images
> to main U-boot.
> 
> Reported-by: Simon Glass <sjg@chromium.org>
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
> ---
>  common/spl/Kconfig                     | 2 +-
>  configs/starfive_visionfive2_defconfig | 1 -
>  configs/th1520_lpi4a_defconfig         | 1 -
>  configs/xilinx_mbv32_defconfig         | 1 -
>  configs/xilinx_mbv32_smode_defconfig   | 1 -
>  configs/xilinx_mbv64_defconfig         | 1 -
>  configs/xilinx_mbv64_smode_defconfig   | 1 -
>  7 files changed, 1 insertion(+), 7 deletions(-)

Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>